{"id":999335,"date":"2026-09-01T09:09:13","date_gmt":"2026-09-01T13:09:13","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-subsystem-for-pcie-6-0-architecture-achieves-first-pass-pci-express-specification-compliance\/"},"modified":"2026-09-01T09:09:13","modified_gmt":"2026-09-01T13:09:13","slug":"cadence-subsystem-for-pcie-6-0-architecture-achieves-first-pass-pci-express-specification-compliance","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-subsystem-for-pcie-6-0-architecture-achieves-first-pass-pci-express-specification-compliance\/","title":{"rendered":"Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance"},"content":{"rendered":"

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Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance<\/b><\/p>\n

Complete x8 subsystem solution in TSMC N3 process demonstrates industry readiness for mass production and de-risks adoption for AI\/HPC customers<\/i><\/b><\/p>\n

SAN JOSE, Calif.–(BUSINESS WIRE<\/a>)–
\nCadence (Nasdaq: CDNS) today announced that its PHY and controller IP for the PCI Express\u00ae<\/sup> (PCIe\u00ae<\/sup>) 6.0 specification, implemented in the TSMC N3 process, achieved first-pass success at the recent PCI-SIG\u00ae<\/sup> compliance workshop held in late July. The workshop marked the industry\u2019s first official event for PCIe 6.0 specification compliance testing, with Cadence\u2019s x8 subsystem solution tested at the full PCIe 6.0 specification speed of 64 GT\/s.<\/p>\n

\nThe complete Cadence subsystem solution, comprising both PHY and controller, successfully passed all official PCIe 6.0 compliance specification tests and is on PCI-SIG\u2019s Integrators List<\/a>.<\/p>\n

\n\u201cPCI Express is a crucial scale-up interconnect for AI\/HPC data centers and AI factories, and Cadence\u2019s subsystem for the PCIe 6.0 specification delivers best-in-class performance with among the lowest power in the industry,\u201d said Marc Loinaz, vice president of research and development for high-performance PHY, Silicon Solutions Group at Cadence. \u201cThis first-pass compliance success validates our complete PHY and controller solution and gives customers confidence that our technology is fully interoperable and ready for production.\u201d<\/p>\n

\nThe milestone underscores the importance of early ecosystem collaboration in bringing new standards to market. Cadence worked closely with PCI-SIG, test equipment providers, and industry partners in the months leading up to the official compliance workshop, conducting interoperability testing to identify and resolve potential issues before the formal evaluation.<\/p>\n

\n\u201cAs PCIe 6.0 technology enables the next wave of AI and high-performance computing systems, rigorous compliance and interoperability testing are essential for ecosystem success,\u201d said Brig Asay, General Manager, Network Data Center, Keysight Technologies. \u201cCadence\u2019s first-pass compliance achievement reflects both the quality of its PCIe 6.0 subsystem implementation and the effectiveness of comprehensive validation using Keysight\u2019s test and measurement solutions. We are pleased to support industry leaders in accelerating PCIe 6.0 technology deployment with confidence.\u201d<\/p>\n

\n\u201cCadence is a long-standing PCI-SIG member helping to further PCIe technology adoption,\u201d said Al Yanes, president and chairperson of PCI-SIG. \u201cCadence\u2019s PCIe 6.0 compliance milestone plays a role in the continued advancement of PCIe technology architecture.\u201d<\/p>\n

\nPCIe 6.0 technology addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems, where the standard is used for accelerator cards, network interfaces, and storage devices. The interface is expected to see wide adoption in data center and AI infrastructure, with broader deployment in automotive and enterprise systems following as the ecosystem matures.<\/p>\n

\n\u201cPositron AI has licensed Cadence\u2019s SerDes IP for the PCIe 6.0 specification for our AI inference accelerator chip,\u201d said Thomas Sohmers, CTO at Positron AI. \u201cCadence\u2019s complete PCIe 6.0 subsystem built in silicon and robust interoperability testing give us confidence that our PCIe 6.0 interface will meet the high-bandwidth connectivity demands of our transformer workloads.\u201d<\/p>\n

\nKey features of Cadence\u2019s PCIe 6.0 technology solution include:<\/p>\n