{"id":969360,"date":"2026-06-02T09:20:40","date_gmt":"2026-06-02T13:20:40","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/"},"modified":"2026-06-02T09:20:40","modified_gmt":"2026-06-02T13:20:40","slug":"xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/","title":{"rendered":"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers"},"content":{"rendered":"<h2>\nStrengthening Microchip Technology\u2019s data center solutions portfolio, the retimers support high\u2011bandwidth architectures while helping reduce integration complexity<br \/>\n<\/h2>\n<div class=\"mw_release\">\n<p align=\"left\">CHANDLER, Ariz., June  02, 2026  (GLOBE NEWSWIRE) &#8212; As AI workloads continue to scale, data center architects are increasingly constrained by limited signal reach and rising latency, which can leave valuable memory resources underutilized across large GPU clusters. These challenges are amplified as interconnect speeds increase. At 64 GT\/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server architectures. In response, Microchip Technology\u00a0<strong>(Nasdaq: MCHP)<\/strong> has released <a href=\"https:\/\/www.microchip.com\/en-us\/products\/storage\/xpressconnect-pcie-gen-6-and-cxl-retimer-family\" rel=\"nofollow\" target=\"_blank\"><strong>XpressConnect\u2122<\/strong><\/a> PCIe<sup>\u00ae<\/sup> 6.0 and CXL<sup>\u00ae<\/sup> 3.1 retimers to enable memory expansion and resource disaggregation in large-scale AI fabrics.<\/p>\n<p align=\"left\">The retimers are designed to extend signal reach beyond conventional PCIe Gen 5 and Gen 6 electrical limits, enabling more flexible system designs across complex baseboards, riser cards and cabled interconnects. The retimers are engineered to help address these challenges by enabling higher\u2011bandwidth connectivity while supporting the stringent thermal and power budgets required in modern AI fabrics. XpressConnect retimers achieve a pin\u2011to\u2011pin latency of less than 12 ns, approximately 80% lower than PCIe 6.0 specifications. This low\u2011latency performance helps improve utilization of AI accelerators and GPUs by reducing data stalls in high\u2011density AI clusters.<\/p>\n<p align=\"left\">\u201cAI data centers are increasingly constrained not by compute, but by the ability to move data efficiently across the system. As PCIe 6.0 pushes speeds to 64 GT\/s, signal reach and latency become critical design challenges,\u201d said Brian McCarson, corporate vice president and GM of Microchip\u2019s data center solutions business unit. \u201cOur XpressConnect retimers are designed to act as the high\u2011performance nerve center of the AI server, helping customers build more scalable, power\u2011efficient fabrics by reducing latency and improving connectivity across dense GPU clusters. This system\u2011level approach allows data center architects to reclaim underutilized resources and improve overall platform efficiency at scale.\u201d<\/p>\n<p align=\"left\">The XpressConnect retimers round out Microchip\u2019s data center portfolio and are engineered to work alongside the company\u2019s 3\u2011nm Switchtec\u2122 PCIe Gen 6 switches, Adaptec<sup>\u00ae<\/sup> SmartRAID controllers and Host Bus Adapters (HBAs) and Flashtec\u2122 NVMe<sup>\u00ae<\/sup> controllers, helping enable a pre\u2011validated, interoperable fabric. Microchip\u2019s XpressConnect PCIe Gen 6 and CXL 3.1 retimers can integrate with PCIe Gen 3, Gen 4 and Gen 5 platforms where required, which helps reduce time to market. The retimers also connect into Microchip\u2019s ChipLink diagnostic ecosystem, delivering a unified graphical user interface for real\u2011time 2D eye capture and four\u2011level pulse amplitude modulation (PAM4) telemetry. These capabilities help data center operators monitor link health more effectively and simplify troubleshooting, which can help reduce total cost of ownership.<\/p>\n<p align=\"left\">Engineered as an industry\u2011standard, drop\u2011in solution, XpressConnect retimers are designed to help reduce the risk of single\u2011vendor dependency for hyperscalers. Additionally, the devices support flexible link bifurcation configurations (1\u00d716, 2\u00d78 and 4\u00d74) and align with widely adopted retimer footprint guidelines, while providing enterprise\u2011class features such as hot\u2011plug support and end\u2011to\u2011end data integrity. Visit the website to learn more about Microchip Technology\u2019s <a href=\"https:\/\/www.microchip.com\/en-us\/solutions\/data-centers-and-computing\/data-center-solutions\" rel=\"nofollow\" target=\"_blank\"><strong>data center solutions<\/strong><\/a> for high\u2011performance compute, storage and connectivity.<\/p>\n<p align=\"left\">\n        <strong>Development Tools<\/strong><br \/>\n        <br \/>Microchip\u2019s ChipLink diagnostic tools offer comprehensive debug, diagnostics, configuration and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment.<\/p>\n<p align=\"left\">\n        <strong>Pricing and Availability<\/strong><br \/>\n        <br \/>The XpressConnect retimers can be\u00a0<a href=\"https:\/\/www.microchipdirect.com\/\" rel=\"nofollow\" target=\"_blank\">purchased<\/a> directly from Microchip or contact a Microchip\u00a0<a href=\"https:\/\/www.microchip.com\/en-us\/about\/global-sales-and-distribution\" rel=\"nofollow\" target=\"_blank\">sales representative or authorized worldwide distributor<\/a>.<\/p>\n<p align=\"left\">\n        <strong>Resources<\/strong><br \/>\n        <br \/>High-res images available through Flickr or editorial contact (feel free to publish):<\/p>\n<ul>\n<li>Application image: <a href=\"https:\/\/www.flickr.com\/gp\/microchiptechnology\/cQr02U0g4J\" rel=\"nofollow\" target=\"_blank\"><strong>https:\/\/www.flickr.com\/gp\/microchiptechnology\/cQr02U0g4J<\/strong><\/a>\n<\/li>\n<\/ul>\n<p align=\"left\">\n        <strong><br \/>\n          <u>About Microchip Technology<\/u><br \/>\n        <\/strong><br \/>\n        <strong>:<\/strong><br \/>\n        <br \/>Microchip Technology Inc. is a broadline supplier of semiconductors committed to making innovative design easier through total system solutions that address critical challenges at the intersection of emerging technologies and durable end markets. Its easy-to-use development tools and comprehensive product portfolio supports customers throughout the design process, from concept to completion. Headquartered in Chandler, Arizona, Microchip offers outstanding technical support and delivers solutions across the industrial, automotive, consumer, aerospace and defense, communications and computing markets. For more information, visit the Microchip website at <a href=\"http:\/\/www.microchip.com\" rel=\"nofollow\" target=\"_blank\"><strong>www.microchip.com<\/strong><\/a>. <\/p>\n<p align=\"left\">\n        <em>Note: The Microchip name and logo, the Microchip logo, and Adaptec are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Switchtec, Flashtec and XpressConnect are trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All other trademarks mentioned herein are the property of their respective companies.<\/em>\n      <\/p>\n<p align=\"left\">\n        <strong>Editorial Contact:<\/strong><br \/>\n        <br \/>Amber Liptai<br \/>480-792-5047<br \/><a href=\"mailto:amber.liptai@microchip.com\" rel=\"nofollow\" target=\"_blank\">amber.liptai@microchip.com<\/a><\/p>\n<p>      <img decoding=\"async\" alt=\"\" class=\"__GNW8366DE3E__IMG\" src=\"https:\/\/www.globenewswire.com\/newsroom\/ti?nf=OTcyODkzMCM3NjI3OTE0IzIwMDQ3NzY=\" \/><br \/>\n      <br \/>\n      <img decoding=\"async\" alt=\"\" src=\"https:\/\/ml.globenewswire.com\/media\/OTdhMWI4OWQtODc2ZC00YmM5LTgxZTMtMjNiNTc2MWYzZjVlLTEwMTYzNDktMjAyNi0wNi0wMi1lbg==\/tiny\/Microchip-Technology-Inc-.png\" \/>\n    <\/div>\n<div class=\"mw_contactinfo\"><\/div>\n","protected":false},"excerpt":{"rendered":"<p>Strengthening Microchip Technology\u2019s data center solutions portfolio, the retimers support high\u2011bandwidth architectures while helping reduce integration complexity CHANDLER, Ariz., June 02, 2026 (GLOBE NEWSWIRE) &#8212; As AI workloads continue to scale, data center architects are increasingly constrained by limited signal reach and rising latency, which can leave valuable memory resources underutilized across large GPU clusters. These challenges are amplified as interconnect speeds increase. At 64 GT\/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server architectures. In response, Microchip Technology\u00a0(Nasdaq: MCHP) has released XpressConnect\u2122 PCIe\u00ae 6.0 and CXL\u00ae 3.1 retimers to enable memory expansion and resource disaggregation in large-scale AI fabrics. The retimers are designed to extend signal reach beyond conventional PCIe Gen 5 and &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers&#8221;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-969360","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Strengthening Microchip Technology\u2019s data center solutions portfolio, the retimers support high\u2011bandwidth architectures while helping reduce integration complexity CHANDLER, Ariz., June 02, 2026 (GLOBE NEWSWIRE) &#8212; As AI workloads continue to scale, data center architects are increasingly constrained by limited signal reach and rising latency, which can leave valuable memory resources underutilized across large GPU clusters. These challenges are amplified as interconnect speeds increase. At 64 GT\/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server architectures. In response, Microchip Technology\u00a0(Nasdaq: MCHP) has released XpressConnect\u2122 PCIe\u00ae 6.0 and CXL\u00ae 3.1 retimers to enable memory expansion and resource disaggregation in large-scale AI fabrics. The retimers are designed to extend signal reach beyond conventional PCIe Gen 5 and &hellip; Continue reading &quot;XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers&quot;\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/\" \/>\n<meta property=\"og:site_name\" content=\"Market Newsdesk\" \/>\n<meta property=\"article:published_time\" content=\"2026-06-02T13:20:40+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.globenewswire.com\/newsroom\/ti?nf=OTcyODkzMCM3NjI3OTE0IzIwMDQ3NzY=\" \/>\n<meta name=\"author\" content=\"Newsdesk\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Newsdesk\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\\\/\"},\"author\":{\"name\":\"Newsdesk\",\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/#\\\/schema\\\/person\\\/482f27a394d4fda80ecb5499e519d979\"},\"headline\":\"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers\",\"datePublished\":\"2026-06-02T13:20:40+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\\\/\"},\"wordCount\":762,\"image\":{\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.globenewswire.com\\\/newsroom\\\/ti?nf=OTcyODkzMCM3NjI3OTE0IzIwMDQ3NzY=\",\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\\\/\",\"url\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\\\/\",\"name\":\"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers - 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These challenges are amplified as interconnect speeds increase. At 64 GT\/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server architectures. In response, Microchip Technology\u00a0(Nasdaq: MCHP) has released XpressConnect\u2122 PCIe\u00ae 6.0 and CXL\u00ae 3.1 retimers to enable memory expansion and resource disaggregation in large-scale AI fabrics. The retimers are designed to extend signal reach beyond conventional PCIe Gen 5 and &hellip; Continue reading \"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers\"","og_url":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/","og_site_name":"Market Newsdesk","article_published_time":"2026-06-02T13:20:40+00:00","og_image":[{"url":"https:\/\/www.globenewswire.com\/newsroom\/ti?nf=OTcyODkzMCM3NjI3OTE0IzIwMDQ3NzY=","type":"","width":"","height":""}],"author":"Newsdesk","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Newsdesk","Est. reading time":"4 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/#article","isPartOf":{"@id":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/"},"author":{"name":"Newsdesk","@id":"https:\/\/www.marketnewsdesk.com\/#\/schema\/person\/482f27a394d4fda80ecb5499e519d979"},"headline":"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers","datePublished":"2026-06-02T13:20:40+00:00","mainEntityOfPage":{"@id":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/"},"wordCount":762,"image":{"@id":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/#primaryimage"},"thumbnailUrl":"https:\/\/www.globenewswire.com\/newsroom\/ti?nf=OTcyODkzMCM3NjI3OTE0IzIwMDQ3NzY=","inLanguage":"en-US"},{"@type":"WebPage","@id":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/","url":"https:\/\/www.marketnewsdesk.com\/index.php\/xpressconnect-pcie-6-0-and-cxl-3-1-retimers-address-latency-and-signal-integrity-challenges-in-ai-data-centers\/","name":"XpressConnect\u2122 PCIe\u00ae 6.0 and CXL 3.1 Retimers Address Latency and Signal\u2011Integrity Challenges in AI Data Centers - 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