{"id":966855,"date":"2026-05-26T09:03:20","date_gmt":"2026-05-26T13:03:20","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/ase-launches-automated-310mm-panel-level-packaging-to-accelerate-ai-innovation\/"},"modified":"2026-05-26T09:03:20","modified_gmt":"2026-05-26T13:03:20","slug":"ase-launches-automated-310mm-panel-level-packaging-to-accelerate-ai-innovation","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/ase-launches-automated-310mm-panel-level-packaging-to-accelerate-ai-innovation\/","title":{"rendered":"ASE Launches Automated 310mm Panel-Level Packaging to Accelerate AI Innovation"},"content":{"rendered":"

<\/p>\n

ASE Launches Automated 310mm Panel-Level Packaging to Accelerate AI Innovation<\/b><\/p>\n

Driving performance, scalability, and efficiency for next-generation compute workloads<\/i><\/p>\n

SUNNYVALE, Calif.–(BUSINESS WIRE<\/a>)–
\nAdvanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711) and a leading provider of semiconductor assembly and test services, today announced the development of an industry-first automated 310mm \u00d7 310mm panel-level packaging production line, advancing its leadership in next-generation advanced packaging technologies. This milestone expands economies of scale by enabling a seamless transition from wafer-level packaging to panel-level packaging while preserving design rule consistency across FOCoS and FOCoS-Bridge packaging platforms. The new panel line is expected to enter production in the first half of 2027.<\/p>\n

\nThe announcement further accentuates ASE\u2019s commitment to enabling the semiconductor industry\u2019s transition into the era of heterogeneous integration, where performance is increasingly defined by high-bandwidth, low-latency interconnects across chiplets, ASICs, and high-bandwidth memory (HBM). As AI accelerators and high-performance computing (HPC) devices grow in complexity, panel-level packaging represents a critical innovation to support the roadmap toward trillion-transistor system-in-package architectures.<\/p>\n

\nASE\u2019s automated panel-level packaging line supports 310mm \u00d7 310mm format and is compatible with advanced packaging platforms including FOCoS and FOCoS-Bridge, delivering line\/space capabilities of 2\/2\u00b5m and 8\/8\u00b5m, respectively. By transitioning from traditional round wafers to rectangular panels, ASE enables significantly greater usable area\u2014up to 96,100 mm2<\/sup> per panel\u2014allowing for more dies per unit and improved material efficiency.<\/p>\n

\nThis shift to panel-level packaging addresses critical industry challenges, including rising interposer sizes and declining wafer-level efficiency. The larger panel format supports higher throughput and reduced cycle time, while enabling integration of increasingly complex multi-die architectures. These benefits are especially impactful for AI data center and HPC applications, where demand for larger package sizes and higher I\/O density continues to accelerate.<\/p>\n

\n\u201cASE is driving a fundamental shift in advanced packaging by introducing an automated panel-level manufacturing platform that significantly improves scalability and efficiency,\u201d said Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE. \u201cThis innovation enables higher integration density and supports the evolving requirements of AI and HPC systems, where performance, power efficiency, and manufacturability must be addressed holistically.\u201d<\/p>\n

\nThe panel-level platform delivers higher throughput through large-area processing and reduced tool change steps, while offering a flexible foundation for heterogeneous integration and system-in-package (SiP) solutions. It supports a wide range of applications including AI, HPC, networking, high-end gaming, and edge AI, helping customers meet performance targets with greater manufacturing efficiency and faster time-to-market.<\/p>\n

\n\u201cPanel-level packaging represents a pivotal step in enabling the next wave of AI-driven innovation,\u201d said Yin Chang, Executive Vice President at ASE. \u201cAs AI training and inference workloads scale, achieving the highest levels of system performance requires not only advanced silicon, but also advances in packaging efficiency and integration. Our panel-level platform enhances throughput, optimizes material utilization, and delivers the scalability needed for increasingly complex computing architectures across a broad range of applications, with hyperscale customers continuing to drive the pace of innovation.\u201d<\/p>\n

\nASE\u2019s new solution also reinforces its competitive differentiation through faster cycle times, scalable manufacturing, and alignment with long-term industry roadmaps for chiplet-based architectures and large-form-factor integration. As the industry moves beyond the limitations of traditional wafer-based processes, ASE continues to lead in delivering advanced packaging solutions that enable new levels of system performance and efficiency.<\/p>\n

\nASE will participate in the 76th IEEE Electronic Components and Technology Conference (ECTC) in Orlando, Florida, from May 26 to May 29, 2026. Dr. Tien Wu, ASE\u2019s Chief Executive Officer, will deliver the plenary keynote titled \u201cAdvanced Packaging & the Future of System Optimization.\u201d Executive Vice President Yin Chang and Corporate Vice President Dr. C. P. Hung will also participate in special panel sessions, covering \u201cEnabling Next-Generation Advanced Packaging Technology \u2013 From Wafer to Panel\u201d and \u201cCo-Design in High-Performance Packaging,\u201d respectively.<\/p>\n

Supporting resources<\/b><\/p>\n