{"id":933212,"date":"2026-02-02T08:34:17","date_gmt":"2026-02-02T13:34:17","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/visionwave-and-boca-jom-ltd-near-completion-of-astradrc-poc-a-patented-automatic-drc-violation-correction-platform-for-advanced-ai-microchips\/"},"modified":"2026-02-02T08:34:17","modified_gmt":"2026-02-02T13:34:17","slug":"visionwave-and-boca-jom-ltd-near-completion-of-astradrc-poc-a-patented-automatic-drc-violation-correction-platform-for-advanced-ai-microchips","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/visionwave-and-boca-jom-ltd-near-completion-of-astradrc-poc-a-patented-automatic-drc-violation-correction-platform-for-advanced-ai-microchips\/","title":{"rendered":"VisionWave and Boca Jom, Ltd. Near Completion of AstraDRC\u2122 POC, a Patented Automatic DRC Violation Correction Platform for Advanced AI Microchips"},"content":{"rendered":"

\nPOC scheduled for demo and evaluation with an AI microchip semiconductor corporation; qSpeed acceleration enables scalable processing of multi-billion-device designs
\n<\/h2>\n
\n

WEST HOLLYWOOD, Calif., Feb. 02, 2026 (GLOBE NEWSWIRE) — VisionWave today announced that, together with its joint-venture partner Boca Jom, Ltd., it is completing a proof-of-concept (POC) release of AstraDRC\u2122, a patented, automated Integrated Circuit (IC) Design Rule Check (DRC) violation correction technology designed to accelerate and streamline advanced semiconductor design. The POC is scheduled for demonstration and evaluation by a major AI microchips semiconductor corporation.<\/p>\n

AstraDRC\u2122 automatically identifies and corrects IC design rule violations while preserving electrical intent and layout integrity\u2014replacing time-consuming, repetitive manual and semi-manual correction loops that can extend tape-out schedules. By reducing the time spent on iterative DRC closure, AstraDRC\u2122 is designed to help teams compress overall design cycle timelines\u2014with the goal of potentially saving months or more on complex programs, particularly for large-scale AI chips.<\/p>\n

In addition to automation, AstraDRC\u2122 introduces layout compaction capabilities as part of its correction methodology\u2014seeking to reduce layout footprint, improve routing efficiency, and support higher silicon utilization. For semiconductor organizations, improved utilization can translate into higher yield per wafer and stronger economics at scale, especially when manufacturing advanced-node devices.<\/p>\n

To support today\u2019s AI-class microchips\u2014often containing billions of devices and extreme rule complexity\u2014VisionWave and Boca Jom, Ltd. leverage the qSpeed\u2122 core accelerator engine, enabling AstraDRC\u2122 to process very large and highly complex designs in practical runtimes. This scalable compute foundation is intended to help semiconductor corporations move faster from design to manufacture, improving productivity without compromising quality.<\/p>\n

\u201cAstraDRC\u2122 represents a step-change in how advanced-node designs can reach DRC closure,\u201d said Dr. Danny Rittman, CTO at VisionWave. \u201cBy combining patented automatic correction with qSpeed acceleration, we\u2019re targeting the largest and most complex AI designs\u2014helping shorten iterative closure loops, improve layout efficiency, and support faster time-to-market with higher confidence.\u201d<\/p>\n

Built for the Full Spectrum of Advanced IC Design<\/p>\n

AstraDRC\u2122 is being developed to support a broad range of design styles and manufacturing requirements, including:<\/p>\n