{"id":924284,"date":"2026-01-06T13:00:52","date_gmt":"2026-01-06T18:00:52","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-launches-partner-ecosystem-to-accelerate-chiplet-time-to-market\/"},"modified":"2026-01-06T13:00:52","modified_gmt":"2026-01-06T18:00:52","slug":"cadence-launches-partner-ecosystem-to-accelerate-chiplet-time-to-market","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-launches-partner-ecosystem-to-accelerate-chiplet-time-to-market\/","title":{"rendered":"Cadence Launches Partner Ecosystem to Accelerate Chiplet Time to Market"},"content":{"rendered":"

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Cadence Launches Partner Ecosystem to Accelerate Chiplet Time to Market<\/b><\/p>\n

Strategic collaborations with Samsung Foundry, Arm and others enable Cadence to deliver pre-validated chiplet solutions based on the Cadence Physical AI chiplet platform<\/i><\/b><\/p>\n

SAN JOSE, Calif.–(BUSINESS WIRE<\/a>)–
\nCadence (Nasdaq: CDNS) today announced a Chiplet Spec-to-Packaged Parts ecosystem to reduce engineering complexity and accelerate time to market for customers developing chiplets targeting physical AI, data center, and high-performance computing (HPC) applications. Initial IP partners joining Cadence include Arm, Arteris, eMemory, M31 Technology, Silicon Creations and Trilinear Technologies, as well as silicon analytics partner proteanTecs. To help reduce risk and streamline customer adoption, Cadence is collaborating with Samsung Foundry to build out a silicon prototype demonstration of the Cadence\u00ae<\/sup> Physical AI chiplet platform, including pre-integrated partner IP on the Samsung Foundry SF5A process.<\/p>\n

This press release features multimedia. View the full release here: https:\/\/www.businesswire.com\/news\/home\/20260106077060\/en\/<\/a><\/p>\n

\"Cadence's<\/p>\n

Cadence’s Chiplet Spec-to-Packaged Parts ecosystem reduces engineering complexity and accelerates time to market for customers developing chiplets targeting physical AI, data center, and HPC applications.<\/p>\n<\/div>\n

\nExtending their longstanding history of close collaboration, Cadence and Arm are working together to accelerate innovation across physical and infrastructure AI applications. Cadence will leverage the advanced Arm\u00ae<\/sup> Zena\u2122<\/sup> Compute Subsystem (CSS) and other essential IP to enhance Cadence\u2019s Physical AI chiplet platform and Chiplet Framework. The resulting new Cadence solutions accommodate the demanding next-generation edge AI processing requirements for automobiles, robotics and drones, as well as the needs of standards-based I\/O and memory chiplets for data center, cloud and HPC applications. The alliances reduce engineering complexities, offer customers a low-risk path to advanced chiplet adoption and pave the way for smarter, safer and more efficient systems.<\/p>\n

\n\u201cCadence\u2019s new chiplet ecosystem represents a significant milestone in chiplet enablement,\u201d said David Glasco, vice president of the Compute Solutions Group at Cadence. \u201cMulti-die and chiplet-based architectures are increasingly critical to achieving greater performance and cost efficiency amid growing design complexity. Cadence\u2019s chiplet solutions optimize costs, provide customization flexibility and enable configurability. By combining our extensive IP and SoC design expertise with pre-integrated and pre-validated IP from our robust partner ecosystem, Cadence is accelerating the development of chiplet-based solutions and helping customers mitigate risk to quickly realize their chiplet ambitions with greater confidence.\u201d<\/p>\n

\nCadence has built spec-driven automation to generate chiplet framework architectures that combine Cadence IP and third-party partner IP with chiplet management, security, and safety features, all supported by advanced software. The generated EDA tool flow enables seamless simulation with the Cadence Xcelium\u2122<\/sup> Logic Simulator and emulation with the Cadence Palladium\u00ae<\/sup> Z3 Enterprise Emulation Platform, while the physical design flow employs real-time feedback for efficient place-and-route cycles. The resulting chiplet architectures are standards-compliant to ensure broad interoperability across the chiplet ecosystem, including adherence to the Arm Chiplet System Architecture and future OCP Foundational Chiplet System Architecture. Cadence\u2019s Universal Chiplet Interconnect Express\u2122<\/sup> (UCIe\u2122<\/sup>) IP provides industry-standard die-to-die connectivity, while a comprehensive protocol IP portfolio enables fast integration of leading-edge interfaces such as LPDDR6\/5X, DDR5-MRDIMM, PCI Express\u00ae<\/sup> (PCIe\u00ae<\/sup>) 7.0, and HBM4.<\/p>\n

\nAn earlier prototype of the Cadence base system chiplet, which is part of the Cadence Physical AI chiplet platform and incorporates the Cadence chiplet framework, UCIe 32G, and LPDDR5X IP, has already been fully silicon validated.<\/p>\n

Supporting Partner Quotes<\/b><\/p>\n

\n\u201cAs compute demands surge across automotive, robotics, and other emerging applications, the industry needs scalable solutions that deliver higher performance, greater efficiency, and functional safety by design. By leveraging Arm Zena CSS, Cadence\u2019s chiplet platform will meet the requirements of next-generation intelligent systems that will advance the physical AI landscape, accelerate chiplet adoption, and help customers reduce design complexity.\u201d<\/p>\n

Suraj Gajendra, Vice President of Products and Solutions, Physical AI Business Unit, Arm<\/i><\/b><\/p>\n

\n\u201cArteris network-on-chip IP products, including Ncore and FlexNoC, are at the forefront of innovation, and we are pleased to support the Cadence Physical AI Chiplet Platform and Chiplet Framework. Together with Cadence, we are enabling customers to confidently adopt chiplet architectures with high-bandwidth, scalable, and production-proven interconnect technology for next-generation multi-die systems.\u201d<\/p>\n

Guillaume Boillet, Vice President of Strategic Marketing, Arteris<\/i><\/b><\/p>\n

\n\u201ceMemory\u2019s enhanced OTP products complement Cadence\u2019s Securyzr\u2122<\/sup> Root of Trust within the Cadence Chiplet Framework. As a leading provider of non-volatile memory technologies, the combination of eMemory technology and Cadence\u2019s security subsystem results in a Physical AI Chiplet platform delivering secure storage and long-lifecycle key management, reinforcing the strong hardware foundation provided by Cadence for die-to-die security and safety in advanced chiplet designs.\u201d<\/p>\n

Charles Hsu, Chairman, eMemory<\/i><\/b><\/p>\n

\n\u201cM31 is proud to be a contributor to Cadence\u2019s expanding chiplet ecosystem, continuously advancing interface IP on leading-edge process technologies and keeping pace with the latest MIPI standards. With proven automotive-grade IP and over a decade of experience supporting high-volume consumer applications, M31 delivers world-class MIPI PHY interface IP that enables customers to rapidly realize advanced chiplet solutions with flexible MIPI CSI and DSI integration.\u201d<\/p>\n

Scott Chang, CEO, M31 Technology<\/i><\/b><\/p>\n

\n\u201cWe\u2019re thrilled to partner with Cadence on its chiplet platform, embedding proteanTecs telemetry across all chiplet types. Together we\u2019re enabling safe, reliable and power-efficient physical AI for next-gen compute demands. It\u2019s an amazing collaboration delivering real value for customers building advanced SoCs and systems for automotive and autonomous applications.\u201d<\/p>\n

Ziv Paz, VP of Business Development, proteanTecs<\/i><\/b><\/p>\n

\n\u201cWe\u2019re pleased to collaborate with Cadence to demonstrate the competitiveness of Samsung\u2019s SF5A technology. Through this trusted partnership, we look forward to the successful expansion of the Chiplet Spec-to-Packaged Parts ecosystem and helping customers accelerate reliable paths to cutting-edge silicon solutions for physical AI applications, including next-generation automotive designs.\u201d<\/p>\n

Taejoong Song, Vice President of Foundry Technology Planning, Samsung Electronics<\/i><\/b><\/p>\n

\n\u201cAs a long-time Cadence partner, we\u2019re pleased to deepen our collaboration through the Chiplet Spec-to-Parts initiative. Over the past 15 years, we\u2019ve developed and delivered over 100 custom PLLs for Cadence across leading foundries. Throughout this partnership, we have provided high-performance low-jitter PLLs and specialized clocking solutions, and we’re excited to extend our collaboration to help accelerate next-generation chiplet-based designs.\u201d<\/p>\n

Pawel Banachowicz, PLL Product Line Development Director, Silicon Creations<\/i><\/b><\/p>\n

\n\u201cTrilinear Technologies is excited to provide our advanced DisplayPort IP as part of this innovative initiative. Collaborating with Cadence enables us to drive high-performance video connectivity and deliver flexible, future-ready display solutions for the chiplet ecosystem.\u201d<\/p>\n

Carl Ruggiero, CEO, Trilinear Technologies<\/i><\/b><\/p>\n

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