{"id":867972,"date":"2025-07-09T10:04:35","date_gmt":"2025-07-09T14:04:35","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-introduces-industry-first-lpddr6-5x-14-4gbps-memory-ip-to-power-next-generation-ai-infrastructure\/"},"modified":"2025-07-09T10:04:35","modified_gmt":"2025-07-09T14:04:35","slug":"cadence-introduces-industry-first-lpddr6-5x-14-4gbps-memory-ip-to-power-next-generation-ai-infrastructure","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-introduces-industry-first-lpddr6-5x-14-4gbps-memory-ip-to-power-next-generation-ai-infrastructure\/","title":{"rendered":"Cadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure"},"content":{"rendered":"

<\/p>\n

Cadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure<\/b><\/p>\n

Integrated subsystem optimized for customer applications including chiplets<\/i><\/p>\n

SAN JOSE, Calif.–(BUSINESS WIRE<\/a>)–
\nCadence (Nasdaq: CDNS) today announced the tapeout of the industry\u2019s first LPDDR6\/5X memory IP system solution optimized to operate at 14.4Gbps, up to 50% faster than the previous generation of LPDDR DRAM. The new Cadence\u00ae<\/sup> LPDDR6\/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers.<\/p>\n

This press release features multimedia. View the full release here: https:\/\/www.businesswire.com\/news\/home\/20250709175651\/en\/<\/a><\/p>\n

\"Cadence<\/p>\n

Cadence LPDDR6\/5X system solution example<\/p>\n<\/div>\n

\nThe Cadence IP for the JEDEC LPDDR6\/5X standard consists of an advanced PHY architecture and a high-performance controller designed to maximize power, performance and area (PPA) while supporting both LPDDR6 and LPDDR5X DRAM protocols for optimal flexibility. The solution supports native integration into traditional monolithic SoCs as well as multi-die system architectures by leveraging the Cadence chiplet framework<\/a>, enabling heterogeneous chiplet integration. The chiplet framework, including the previous LPDDR generation, was successfully taped out<\/a> in 2024.<\/p>\n

\n\u201cThe evolution of data centers from HPC compute virtualization to AI training and inference at scale has driven a massive buildout of AI infrastructure, and designing for efficient data movement via memory interfaces has never been more crucial. LPDDR6 has emerged as a key enabler of accelerated compute, providing the speed, bandwidth, power profile and capacity needed to efficiently perform AI inference,\u201d said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. \u201cWith this tapeout, Cadence is continuing our track record of memory IP leadership by offering an industry-first LPDDR6 implementation delivered as an integrated subsystem optimized for customer applications.\u201d<\/p>\n

\nThe complete PHY and controller memory system boasts a new high-performance, scalable and adaptable architecture based on Cadence\u2019s proven and highly successful DDR5 12.8Gbps, LPDDR5X 10.7Gbps and GDDR7-36G product lines. This first offering in Cadence\u2019s new LPDDR6 IP product line supports the LPDDR6 and LPDDR5X standards, including LPDDR5X CAMM2.<\/p>\n

\nSuitable for the AI, mobile, consumer, enterprise HPC and cloud data center markets, the advanced LPDDR6\/5X memory IP system solution allows maximum flexibility for end products with a range of performance, capacity and cost targets\u2014ensuring long production runs. The LPDDR6\/5X PHY is customizable for different package and system topologies and available as a drop-in hardened macro. This ensures fast and reliable integration, translating into rapid time to market.<\/p>\n

\nThe Cadence LPDDR6\/5X controller includes a full set of industry-standard and advanced features for memory interfaces, such as support for the Arm\u00ae<\/sup> AMBA\u00ae<\/sup> AXI bus. The memory controller is provided as a soft RTL macro for maximum flexibility in features, power, area and performance.<\/p>\n

\nThe Cadence LPDDR6 solution includes the LPDDR6 Memory Model<\/a>,<\/a> which enables engineers to perform comprehensive verification and ensure that system-on-chip (SoC) designs are compatible with the latest JEDEC interface standard, accelerating their adoption of this new technology with confidence. The LPDDR6 Memory Model includes a complete set of protocol checks, functional coverage and a verification plan.<\/p>\n

\nAvailable now for customer engagements, the new LPDDR6\/5X IP is the latest addition to Cadence\u2019s comprehensive family of memory IP system solutions, which also includes DDR, GDDR and HBM. Cadence Memory IP<\/a> is designed with the company\u2019s industry-leading analog\/mixed-signal design tools<\/a>. When combined with Cadence\u2019s UCIe\u2122<\/sup>-based chiplet framework, the new LPDDR6\/5X IP and Cadence\u2019s other leading memory and interface IP deliver an optimized solution that enables rapid chiplet realization. For more information on the new LPDDR6\/5X IP, please visit the LPDDR landing page<\/a> on cadence.com.<\/p>\n

About Cadence<\/b><\/p>\n

\nCadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence\u2019s Intelligent System Design\u2122<\/sup> strategy, are essential for the world\u2019s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world\u2019s top 100 best-managed companies. Cadence solutions offer limitless opportunities\u2014learn more at www.cadence.com<\/a>.<\/p>\n

\u00a9 2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at <\/i>www.cadence.com\/go\/trademarks<\/i><\/a> are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm and AMBA are registered trademarks of Arm Limited (or its subsidiaries) in the US and\/or elsewhere. UCIe is a trademark of UCIe Consortium. All other trademarks are the property of their respective owners.<\/i><\/p>\n

\nCategory: Featured<\/p>\n

\"\"<\/p>\n

View source version on businesswire.com: <\/span>https:\/\/www.businesswire.com\/news\/home\/20250709175651\/en\/<\/a><\/span><\/p>\n

For more information, please contact:
\n<\/b>
Cadence Newsroom
\n
408-944-7039
\n
newsroom@cadence.com<\/a><\/p>\n

KEYWORDS:<\/b> United States North America California<\/p>\n

INDUSTRY KEYWORDS:<\/b> Data Management Technology Semiconductor Apps\/Applications Software Artificial Intelligence Networks Internet Mobile\/Wireless Hardware Electronic Design Automation<\/p>\n

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Cadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure Integrated subsystem optimized for customer applications including chiplets SAN JOSE, Calif.–(BUSINESS WIRE)– Cadence (Nasdaq: CDNS) today announced the tapeout of the industry\u2019s first LPDDR6\/5X memory IP system solution optimized to operate at 14.4Gbps, up to 50% faster than the previous generation of LPDDR DRAM. The new Cadence\u00ae LPDDR6\/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers. This press release features multimedia. View the full release here: … <\/p>\n

Continue reading “Cadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-867972","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"\nCadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-introduces-industry-first-lpddr6-5x-14-4gbps-memory-ip-to-power-next-generation-ai-infrastructure\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Cadence Introduces Industry-First LPDDR6\/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure Integrated subsystem optimized for customer applications including chiplets SAN JOSE, Calif.–(BUSINESS WIRE)– Cadence (Nasdaq: CDNS) today announced the tapeout of the industry\u2019s first LPDDR6\/5X memory IP system solution optimized to operate at 14.4Gbps, up to 50% faster than the previous generation of LPDDR DRAM. The new Cadence\u00ae LPDDR6\/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers. This press release features multimedia. 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The new Cadence\u00ae LPDDR6\/5X memory IP system solution is a key enabler for scaling up the AI infrastructure to accommodate the memory bandwidth and capacity demands of next-generation AI LLMs, agentic AI and other compute-heavy workloads for various verticals. Multiple engagements are currently underway with leading AI, high-performance computing (HPC) and data center customers. This press release features multimedia. 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