{"id":840499,"date":"2025-04-23T07:14:05","date_gmt":"2025-04-23T11:14:05","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/quicklogic-to-present-and-exhibit-at-andes-risc-v-con-technology-summit-in-san-jose\/"},"modified":"2025-04-23T07:14:05","modified_gmt":"2025-04-23T11:14:05","slug":"quicklogic-to-present-and-exhibit-at-andes-risc-v-con-technology-summit-in-san-jose","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/quicklogic-to-present-and-exhibit-at-andes-risc-v-con-technology-summit-in-san-jose\/","title":{"rendered":"QuickLogic to Present and Exhibit at Andes RISC-V CON Technology Summit in San Jose"},"content":{"rendered":"
\n

PR Newswire<\/p>\n<\/p><\/div>\n

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\n SAN JOSE, Calif.<\/span>
\n <\/span>, April 23, 2025<\/span><\/span> \/PRNewswire\/ — QuickLogic Corporation (NASDAQ: QUIK), a developer of embedded FPGA (eFPGA) Hard IP, ruggedized FPGAs, and FPGA User Tools, will present and exhibit at the Andes RISC-V CON Technology Summit in San Jose<\/span> on April 29<\/span>th<\/sup>. The presentation, delivered by QuickLogic’s Vice President of IP Sales, Andy Jaros<\/span>, will focus on using embedded FPGA<\/a> (eFPGA) technology to customize embedded RISC-V processing solutions from Andes Technology.<\/p>\n

\n

\n
\n \"QuickLogic
\n <\/a>\n <\/p>\n<\/p><\/div>\n

\n\n\n\n\n\n
\n

\n Title:<\/span>\n <\/p>\n<\/td>\n

\n

\n RISC-V + eFPGA: A Flexible Solution for Any Application<\/span>\n <\/p>\n<\/td>\n<\/tr>\n

\n

\n Date:<\/span>\n <\/p>\n<\/td>\n

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\n April 29, 2025<\/span>\n <\/p>\n<\/td>\n<\/tr>\n

\n

\n Time:<\/span>\n <\/p>\n<\/td>\n

\n

\n 12:10 p.m. PT<\/span>\n <\/p>\n<\/td>\n<\/tr>\n

\n

\n Venue:<\/span>\n <\/p>\n<\/td>\n

\n

\n DoubleTree by Hilton San Jose<\/span>\n <\/p>\n<\/td>\n<\/tr>\n<\/table><\/div>\n

Mr. Jaros will discuss multiple use cases for augmenting processor-based designs with complementary eFPGA capabilities, including acceleration, co-processing, and peripheral integration. For each case, he will explain the inherent flexibility benefits in eFPGA technology and how these attributes can significantly add value to ASIC<\/span>-based embedded processor designs.<\/p>\n

He will also discuss QuickLogic’s Australis\u2122 eFPGA IP Generator, highlighting how QuickLogic rapidly creates custom eFPGA Hard IP cores tailored to each customer’s unique requirements, across a wide range of process technologies and nodes.<\/p>\n

In addition to the presentation,\u00a0QuickLogic will be exhibiting at the event to engage with attendees and share more about its eFPGA solutions. For more information, please visit the event website<\/a>.<\/p>\n

\n About QuickLogic\u00a0
<\/b>QuickLogic Corporation is a fabless semiconductor company that specializes in eFPGA Hard IP, discrete FPGAs, and endpoint AI solutions. The company’s unique technology, combined with open-source development tools, enables highly customizable and low-power silicon solutions for aerospace and defense, industrial, consumer, and edge computing markets. For more information, visit www.quicklogic.com<\/a>.<\/p>\n

\n About Andes Technology
<\/b>As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology\u00a0(TWSE: 6533<\/a>;\u00a0SIN: US03420C2089<\/a>;\u00a0ISIN: US03420C1099<\/a>) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters.\u00a0With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware\/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices.\u00a0Over\u00a016 billion Andes-powered SoCs\u00a0are driving innovations globally. Discover more at\u00a0www.andestech.com<\/a>\u00a0and connect with Andes on\u00a0LinkedIn<\/a>,\u00a0X (formerly Twitter)<\/a>,\u00a0Bilibili<\/a>\u00a0and\u00a0YouTube<\/a>.<\/p>\n

\n QuickLogic and logo are registered trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.<\/i>\u00a0\u00a0<\/p>\n

\u00a0<\/p>\n

\n \"Cision\" View original content to download multimedia:https:\/\/www.prnewswire.com\/news-releases\/quicklogic-to-present-and-exhibit-at-andes-risc-v-con-technology-summit-in-san-jose-302435536.html<\/a><\/p>\n

SOURCE QuickLogic Corporation<\/p>\n<\/p><\/div>\n

\"\"<\/p>\n","protected":false},"excerpt":{"rendered":"

PR Newswire SAN JOSE, Calif. , April 23, 2025 \/PRNewswire\/ — QuickLogic Corporation (NASDAQ: QUIK), a developer of embedded FPGA (eFPGA) Hard IP, ruggedized FPGAs, and FPGA User Tools, will present and exhibit at the Andes RISC-V CON Technology Summit in San Jose on April 29th. The presentation, delivered by QuickLogic’s Vice President of IP Sales, Andy Jaros, will focus on using embedded FPGA (eFPGA) technology to customize embedded RISC-V processing solutions from Andes Technology. Title: RISC-V + eFPGA: A Flexible Solution for Any Application Date: April 29, 2025 Time: 12:10 p.m. PT Venue: DoubleTree by Hilton San Jose Mr. Jaros will discuss multiple use cases for augmenting processor-based designs with complementary eFPGA capabilities, including acceleration, co-processing, and peripheral integration. … <\/p>\n

Continue reading “QuickLogic to Present and Exhibit at Andes RISC-V CON Technology Summit in San Jose”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-840499","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"\nQuickLogic to Present and Exhibit at Andes RISC-V CON Technology Summit in San Jose - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/quicklogic-to-present-and-exhibit-at-andes-risc-v-con-technology-summit-in-san-jose\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"QuickLogic to Present and Exhibit at Andes RISC-V CON Technology Summit in San Jose - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"PR Newswire SAN JOSE, Calif. , April 23, 2025 \/PRNewswire\/ — QuickLogic Corporation (NASDAQ: QUIK), a developer of embedded FPGA (eFPGA) Hard IP, ruggedized FPGAs, and FPGA User Tools, will present and exhibit at the Andes RISC-V CON Technology Summit in San Jose on April 29th. The presentation, delivered by QuickLogic’s Vice President of IP Sales, Andy Jaros, will focus on using embedded FPGA (eFPGA) technology to customize embedded RISC-V processing solutions from Andes Technology. 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