{"id":832402,"date":"2025-04-01T12:41:46","date_gmt":"2025-04-01T16:41:46","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/ase-demonstrates-cpo-that-improves-energy-efficiency-for-ai-applications\/"},"modified":"2025-04-01T12:41:46","modified_gmt":"2025-04-01T16:41:46","slug":"ase-demonstrates-cpo-that-improves-energy-efficiency-for-ai-applications","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/ase-demonstrates-cpo-that-improves-energy-efficiency-for-ai-applications\/","title":{"rendered":"ASE Demonstrates CPO that Improves Energy Efficiency for AI applications"},"content":{"rendered":"

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ASE Demonstrates CPO that Improves Energy Efficiency for AI applications<\/b><\/p>\n

SUNNYVALE, Calif.–(BUSINESS WIRE<\/a>)–
\nAdvanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711), today announced that it has demonstrated a co-packaged optics (CPO) device that mounts multiple optical engines (OE) directly onto a substrate, enabling <5pJ\/bit power consumption and significant bandwidth increases. With today\u2019s processing power requirements being extremely amplified by AI pervasion, there is unprecedented demand for bandwidth that must be addressed. ASE\u2019s new configuration enables crucial on-package energy efficiency and bandwidth expansion while addressing further data center challenges by delivering improvement related to latency, data throughput, and scalability.\n<\/p>\n

\nAccording to IDC (Jan 2025), the proliferation of AI silicon in the data center will experience 24.9% CAGR from 2024 to 2028 in support of capacity demand and infrastructure growth, hence elevating the need for new energy efficiencies. Advanced packaging creativity is bringing the OE directly into the switch silicon package to generate the shortest possible electrical traces resulting in consequential power savings. ASE\u2019s configuration results in shorter electrical path and lower insertion loss, as well as improved power efficiency. The CPO structure is a key interim step in ASE\u2019s progression from pluggable options to optical IO and fully integrated 3D CPO. A major milestone for ASE has been the development the CPO assembly process flow, substrate warpage and coplanarity control to meet fiber array coupling requirement, and structure and warpage synergy for both edge (horizontal) and surface (vertical) fiber coupling. All these areas are critical to ensuring optimized data throughput while minimizing optical related losses.\n<\/p>\n

\nAs bandwidth demands grow exponentially, the current faceplate-pluggable (FPP) solutions show roadmap limitations in density, power, and cost. The increasing switch speeds also lead to an increase in SerDes interconnect power as a percentage of the total switch power. This is driving the need to move the optics from the FPP into the enclosure closer to the switch ASIC. On-board optics have been adopted as a first step, and ASE\u2019s CPO provides an attractive option that has lower insertion loss, resulting in reduced power consumption and cost\/bit. From a pJ\/bit comparison, FPP solutions are currently 30pJ\/bit, while on-board solutions are 20pJ\/bit, but now scaling <5pJ\/bit through CPO.\n<\/p>\n

\nASE\u2019s CPO solves the assembly challenge of multiple optical engines with an ASIC in an integrated package with a large body configuration of >75mm X 75mm. The benefits for both the networking and data center markets are significant. For networking, it provides a potential option to improve or replace pluggable optics at 1.6Tb\/s or 3.2 Tb\/s, as well as an integration solution that enables ultra-low latency option for CPO. For compute, the platform can be used to integrate the CPUs, GPUs, XPUs with the optics into a single co-packaged solution through high-speed optical data links.\n<\/p>\n

\n\u201cGlobal demand for data center capacity could rise at 27% CAGR from 2023 to 2030 to reach an annual demand of 298 GigaWatts (GW), according to 2025 report from McKinsey. Such tremendous growth represents a sharp increase from the current demand of 60 GW and signals a potential supply gap. This is why ASE is committed to bring power efficiencies to the data center though our CPO innovation,\u201d said Dr. CP Hung, Vice President of Research & Development, ASE. \u201cIt\u2019s well documented that the main driving force for CPO technology is its ability to lower energy consumption and deliver economic advantage. Our CPO places the optical engine very close to the ASIC chip, meaning link loss is reduced and there is no need for a re-timer chip to compensate for the signal between the two. This leads to significant reduction of its energy consumption, and a big improvement in the overall bandwidth density of the system.\u201d\n<\/p>\n

\n\u201cOur industry has moved beyond classical compute into the high-performance compute era where data center demands are being highly influenced by advanced AI models and applications, power consumption, and ongoing cloud and edge compute dynamics,\u201d added Yin Chang, Executive Vice President, ASE. \u201cThese present massive challenges, particularly related to power and cooling limitations, and require our industry to deliver breakthrough innovations that facilitate application and scale. At ASE, we are committed to taking silicon photonics to a new level and augmenting our customer value through delivering CPO technology that demonstrates superior energy efficiency at this critical juncture in AI permeation.\u201d\n<\/p>\n

\nASE\u2019s CPO is part of VIPack\u2122, which is a scalable platform expanding in alignment with industry roadmaps, and supported by its Integrated Design Ecosystem\u2122 (IDE), a collaborative design toolset optimized to systematically boost advanced package architecture.\n<\/p>\n

\nASE will be represented at the Optical Fiber Conference 2025 in San Francisco\u00a0 this week\u00a0 by Dr. CP Hung, VP of R&D, who will deliver a presentation titled, \u2018Latest Advanced Packaging Solutions for AI\u2019, scheduled for Thursday April 3rd<\/sup> 15:15 – 15:45 in the Packaging and Coupling Techniques session.\n<\/p>\n

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