{"id":766715,"date":"2023-06-28T10:48:09","date_gmt":"2023-06-28T14:48:09","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-delivers-certified-innovative-backside-implementation-flow-to-support-samsung-foundry-sf2-technology\/"},"modified":"2023-06-28T10:48:09","modified_gmt":"2023-06-28T14:48:09","slug":"cadence-delivers-certified-innovative-backside-implementation-flow-to-support-samsung-foundry-sf2-technology","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-delivers-certified-innovative-backside-implementation-flow-to-support-samsung-foundry-sf2-technology\/","title":{"rendered":"Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology"},"content":{"rendered":"<p>        <!--.bwalignc { text-align: center; list-style-position: inside }\n.bwlistdisc { list-style-type: disc }body {font:normal small Arial,Helvetica,sans-serif;color:#000;background-color:#fff;padding:24px;margin:0;} a img {border:0;} h3 {font-size:medium;color:#000;margin:0 0 1em 0; text-align:center;}-->  <\/p>\n<p class=\"bwalignc\"><b>Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology<\/b><\/p>\n<p><i>Highlights:<\/i><\/p>\n<ul class=\"bwlistdisc\">\n<li><i>Complete backside routing solutions enable next-generation high-performance chips for mobile, automotive, AI and hyperscale applications<\/i><\/li>\n<li><i>Cadence SF2 digital full flow includes advanced technology for nTSV optimization<\/i><\/li>\n<li><i>Backside implementation flow already proven with a successful SF2 test chip tapeout<\/i><\/li>\n<\/ul>\n<p>SAN JOSE, Calif.&#8211;(<a href=\"http:\/\/www.businesswire.com\">BUSINESS WIRE<\/a>)&#8211;<br \/>\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry\u2019s SF2 process node. This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence<sup>\u00ae<\/sup> digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation. The flow has already been validated with the completion of a successful 2nm test chip tapeout.<\/p>\n<p>\nThe complete Cadence RTL-to-GDS flow that is optimized for the Samsung Foundry 2nm process technology includes the Genus<sup>\u2122<\/sup> Synthesis Solution, Innovus<sup>\u2122<\/sup> Implementation System, Integrity<sup>\u2122<\/sup> 3D-IC platform, Quantus<sup>\u2122<\/sup> Extraction Solution, Pegasus<sup>\u2122<\/sup> Verification System, Voltus<sup>\u2122<\/sup> IC Power Integrity Solution, Tempus<sup>\u2122<\/sup> Timing Signoff Solution and Tempus ECO Option. Backside routing improves PPA results and reduces congestion on the frontside layers and can be used for power distribution networks, clock tree nets and signal routing. Accordingly, the four Innovus Implementation System engines have been optimized for the Samsung Foundry 2nm process:<\/p>\n<ul class=\"bwlistdisc\">\n<li>\nInnovus GigaPlace engine automatically places and legalizes a nano through silicon via (nTSV) structure, allowing a connection between frontside and backside layers<\/p>\n<\/li>\n<li>\nInnovus GigaOpt engine uses backside layers for timing-critical long wires to improve chip performance<\/p>\n<\/li>\n<li>\nInnovus NanoRoute engine inherently supports backside routing based on rules in the technology\u2019s Library Exchange Format (LEF)<\/p>\n<\/li>\n<\/ul>\n<p>\nIn addition to the Innovus Implementation System engine capabilities that support SF2 technology, the Quantus Extraction Solution fully supports backside layers to enable the Tempus Timing Solution to sign off designs with a mix of frontside and backside layers, delivering reduced voltage drop on the power distribution mesh and improved routability on the frontside metal layers.<\/p>\n<p>\n\u201cThrough our ongoing collaborations with Cadence, we\u2019re consistently looking for new ways to help our mutual customers accelerate next-generation design innovation,\u201d said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. \u201cThe successful rollout of this backside design flow, fully supported by the Cadence digital flow, lets customers reap the benefits of our advanced SF2 technology.\u201d<\/p>\n<p>\n\u201cDesigners can speed time to market by leveraging our collaboration with Samsung Foundry on the complete RTL-to-GDS flow and SF2 technology,\u201d said Vivek Mishra, corporate vice president in the Digital &amp; Signoff Group at Cadence. \u201cWe\u2019ve already seen a successful tapeout, and we\u2019re looking forward to seeing our customers achieve many more design successes using our latest technologies.\u201d<\/p>\n<p>\nTo learn more about Cadence\u2019s advanced-node digital solutions, visit <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fwww.cadence.com%2Fgo%2Fadvnddigitalsf2&amp;esheet=53435317&amp;newsitemid=20230628148124&amp;lan=en-US&amp;anchor=www.cadence.com%2Fgo%2Fadvnddigitalsf2&amp;index=1&amp;md5=d7f50b1f51b0d9c8368c7bd67ebe3d31\">www.cadence.com\/go\/advnddigitalsf2<\/a>.<\/p>\n<p><b>About Cadence<\/b><\/p>\n<p>\nCadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world\u2019s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fwww.cadence.com&amp;esheet=53435317&amp;newsitemid=20230628148124&amp;lan=en-US&amp;anchor=cadence.com&amp;index=2&amp;md5=a3f7ea06e3ca0ec72789989708d39852\">cadence.com<\/a>.<\/p>\n<p><i>\u00a9 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at <\/i><a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fwww.cadence.com%2Fgo%2Ftrademarks&amp;esheet=53435317&amp;newsitemid=20230628148124&amp;lan=en-US&amp;anchor=www.cadence.com%2Fgo%2Ftrademarks&amp;index=3&amp;md5=a44a6e299523b007447e75356007e017\"><i>www.cadence.com\/go\/trademarks<\/i><\/a><i> are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.<\/i><\/p>\n<p><i>Category: Featured<\/i><\/p>\n<p><img decoding=\"async\" alt=\"\" src=\"https:\/\/cts.businesswire.com\/ct\/CT?id=bwnews&amp;sty=20230628148124r1&amp;sid=flmnd&amp;distro=nx&amp;lang=en\" style=\"width:0;height:0\" \/><span class=\"bwct31415\" \/><\/p>\n<p id=\"mmgallerylink\"><span id=\"mmgallerylink-phrase\">View source version on businesswire.com: <\/span><span id=\"mmgallerylink-link\"><a href=\"https:\/\/www.businesswire.com\/news\/home\/20230628148124\/en\/\" rel=\"nofollow\">https:\/\/www.businesswire.com\/news\/home\/20230628148124\/en\/<\/a><\/span><\/p>\n<p>\nCadence Newsroom<br \/>\n<br \/>408-944-7039<br \/>\n<br \/><a rel=\"nofollow\" href=\"mailto:newsroom@cadence.com\">newsroom@cadence.com<\/a><\/p>\n<p><b>KEYWORDS:<\/b> United States North America California<\/p>\n<p><b>INDUSTRY KEYWORDS:<\/b> Semiconductor Electronic Design Automation Technology Artificial Intelligence Software<\/p>\n<p><b>MEDIA:<\/b><\/p>\n<table cellpadding=\"3\" cellspacing=\"3\">\n<tr>\n<td><font face=\"Arial\" size=\"2\"><b>Logo<\/b><\/font><\/td>\n<\/tr>\n<tr>\n<td><img decoding=\"async\" src=\"https:\/\/mms.businesswire.com\/media\/20230628148124\/en\/633339\/3\/Cadence_Logo_2_Reg_Black.jpg\" alt=\"Logo\" \/><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\"><\/font><\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology Highlights: Complete backside routing solutions enable next-generation high-performance chips for mobile, automotive, AI and hyperscale applications Cadence SF2 digital full flow includes advanced technology for nTSV optimization Backside implementation flow already proven with a successful SF2 test chip tapeout SAN JOSE, Calif.&#8211;(BUSINESS WIRE)&#8211; Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry\u2019s SF2 process node. This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence\u00ae digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation. The flow has already been &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-delivers-certified-innovative-backside-implementation-flow-to-support-samsung-foundry-sf2-technology\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology&#8221;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-766715","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-delivers-certified-innovative-backside-implementation-flow-to-support-samsung-foundry-sf2-technology\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology Highlights: Complete backside routing solutions enable next-generation high-performance chips for mobile, automotive, AI and hyperscale applications Cadence SF2 digital full flow includes advanced technology for nTSV optimization Backside implementation flow already proven with a successful SF2 test chip tapeout SAN JOSE, Calif.&#8211;(BUSINESS WIRE)&#8211; Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry\u2019s SF2 process node. This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence\u00ae digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation. 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(Nasdaq: CDNS) today announced that it has delivered a complete, certified backside implementation flow to support Samsung Foundry\u2019s SF2 process node. This latest collaboration between Cadence and Samsung Foundry enables customers to leverage the Cadence\u00ae digital full flow and corresponding process design kit (PDK) to speed next-generation mobile, automotive, AI and hyperscale chip design innovation. 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