{"id":761592,"date":"2023-06-05T09:03:17","date_gmt":"2023-06-05T13:03:17","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/powervia-test-shows-industry-leading-performance\/"},"modified":"2023-06-05T09:03:17","modified_gmt":"2023-06-05T13:03:17","slug":"powervia-test-shows-industry-leading-performance","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/powervia-test-shows-industry-leading-performance\/","title":{"rendered":"PowerVia Test Shows Industry-Leading Performance"},"content":{"rendered":"<p>        <!--.bwalignc { text-align: center; list-style-position: inside }\n.bwmarginl1 { margin-left: 30px }body {font:normal small Arial,Helvetica,sans-serif;color:#000;background-color:#fff;padding:24px;margin:0;} a img {border:0;} h3 {font-size:medium;color:#000;margin:0 0 1em 0; text-align:center;}-->  <\/p>\n<p class=\"bwalignc\"><b>PowerVia Test Shows Industry-Leading Performance<\/b><\/p>\n<p class=\"bwalignc\"><b>Intel is first to implement backside power in a product-like chip, resulting in over 90% cell utilization and other gains<\/b><\/p>\n<p>SANTA CLARA, Calif.&#8211;(<a href=\"http:\/\/www.businesswire.com\">BUSINESS WIRE<\/a>)&#8211;<b>What\u2019s New:<\/b> Intel is the first in the industry to implement backside power delivery on a product-like test chip, achieving the performance needed to propel the world into the next era of computing. PowerVia, which will be introduced on the Intel 20A process node in the first half of 2024, is Intel\u2019s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer.<\/p>\n<p id=\"news-body-cta\">This press release features multimedia. View the full release here: <a href=\"https:\/\/www.businesswire.com\/news\/home\/20230605005191\/en\/\" rel=\"nofollow\">https:\/\/www.businesswire.com\/news\/home\/20230605005191\/en\/<\/a><\/p>\n<div id=\"bwbodyimg\" style=\"width: 480px;float:left;padding-left:0px;padding-right:20px;padding-top:0px;padding-bottom:0px\"><img decoding=\"async\" src=\"https:\/\/mms.businesswire.com\/media\/20230605005191\/en\/1810038\/4\/Intel-Power-Via-Test-chips-1.jpg\" alt=\"\u200bA wafer holds Blue Sky Creek test chips. The production test helps Intel refine Intel\u2019s PowerVia backside power technology. Expected as part of the Intel 20A manufacturing node in 2024, PowerVia will be the industry\u2019s first implementation of backside power in silicon, solving decades of interconnect bottlenecks. (Credit: Intel Corporation)\" \/><\/p>\n<p style=\"font-size:85%\">\u200bA wafer holds Blue Sky Creek test chips. The production test helps Intel refine Intel\u2019s PowerVia backside power technology. Expected as part of the Intel 20A manufacturing node in 2024, PowerVia will be the industry\u2019s first implementation of backside power in silicon, solving decades of interconnect bottlenecks. (Credit: Intel Corporation)<\/p>\n<\/div>\n<p class=\"bwmarginl1\"><i>\u201cPowerVia is a major milestone in our aggressive \u2018five nodes in four years\u2019 strategy and on our path to achieving a trillion transistors in a package in 2030. Using a trial process node and subsequent test chip enabled us to de-risk backside power for our leading process nodes, placing Intel a node ahead of competitors in bringing backside power delivery to market.\u201d<br \/>\n<br \/><\/i>\u2013Ben Sell, Intel vice president of Technology Development<\/p>\n<p><b>How It Works:<\/b> Intel decoupled development of PowerVia from transistor development to ensure its readiness for silicon implementation based on Intel 20A and Intel 18A process nodes. PowerVia was tested on its own internal test node to debug and ensure good functionality of the technology before its integration with RibbonFET in Intel 20A. After fabrication and testing on a silicon test chip, PowerVia was confirmed to bring a remarkably efficient use of chip resources with greater than 90% cell utilization and major transistor scaling, enabling chip designers to achieve performance and efficiency gains in their products.<\/p>\n<p>\nIntel will present these findings in two papers at the VLSI Symposium on June 11-16 in Kyoto, Japan.<\/p>\n<p><b>Why It Matters:<\/b> PowerVia is well ahead of competitors\u2019 backside power solutions, giving chip designers \u2013 including Intel Foundry Services (IFS) customers \u2013 a faster path to valuable energy and performance gains in their products. Intel has a long track record of introducing the industry\u2019s most critical new technologies, such as strained silicon, Hi-K metal gate and FinFET, to propel <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fnewsroom%2Fresources%2Fmoores-law.html&amp;esheet=53412912&amp;newsitemid=20230605005191&amp;lan=en-US&amp;anchor=Moore%26%238217%3Bs+Law&amp;index=1&amp;md5=ccba27e1aeb1d1a1071e5bcb180b8bdb\">Moore\u2019s Law<\/a> forward. With PowerVia and RibbonFET gate-all-around technology coming in 2024, Intel continues to lead the industry in chip design and process innovations.<\/p>\n<p>\nPowerVia is the first to solve the growing interconnect bottleneck issue for chip designers. Surging use cases, including artificial intelligence and graphics, require smaller, denser and more powerful transistors to meet ever-growing computing demands. Today and for the past many decades, power and signal lines within a transistor\u2019s architecture have competed for the same resources. By separating the two, chips can increase performance and energy-efficiency, and deliver better results for customers. Backside power delivery is vital to transistor scaling, enabling chip designers to increase transistor density without sacrificing resources to deliver more power and performance than ever.<\/p>\n<p><b>How We are Doing It:<\/b> Intel 20A and Intel 18A will introduce both PowerVia backside power technology and RibbonFET gate-all-around technology. As a completely new way of delivering power to the transistors, backside power implementation raised new challenges for thermals and debugging designs.<\/p>\n<p>\nBy decoupling development of PowerVia from RibbonFET, Intel could work through those challenges quickly to ensure readiness for implementation in silicon based on Intel\u2019s 20A and 18A process nodes. Intel engineers developed mitigation techniques to prevent the thermals from becoming an issue. The debug community also developed new techniques to ensure the new design structure could be appropriately de-bugged. As a result, the test implementation delivered solid yield and reliability metrics while demonstrating the intrinsic value proposition of the technology well before it joins new RibbonFET architecture.<\/p>\n<p>\nThe test also leveraged design rules enabled by EUV (extreme ultraviolet) lithography, which produced results including standard cell utilization of more than 90% over large areas of the die, enabling greater cell density, which can be expected to lower costs. The test also showed more than 30% platform voltage droop improvement and 6% frequency benefit. Intel also achieved thermal characteristics in the PowerVia test chip in line with higher power densities expected from logic scaling.<\/p>\n<p><b>What&#8217;s Next:<\/b> In a third paper to be presented during VLSI, Intel technologist Mauro Kobrinsky will explain Intel&#8217;s research into more advanced methods to deploy PowerVia, such as enabling both signaling and power delivery on either the front or the back side of the wafer.<\/p>\n<p>\nBringing PowerVia to customers ahead of the industry and continuing to innovate into the future is in keeping with Intel\u2019s long history of being first to bring new semiconductor innovations to market while constantly innovating.<\/p>\n<p><b>More Context: <\/b><a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fnewsroom%2Fnews%2Fpowervia-intel-achieves-chipmaking-breakthrough.html&amp;esheet=53412912&amp;newsitemid=20230605005191&amp;lan=en-US&amp;anchor=With+PowerVia%2C+Intel+Achieves+a+Chipmaking+Breakthrough&amp;index=2&amp;md5=3e569b92d0f711664bd05b373f659e04\">With PowerVia, Intel Achieves a Chipmaking Breakthrough<\/a><\/p>\n<p><b>About Intel<\/b><\/p>\n<p>\nIntel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore\u2019s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers\u2019 greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better. To learn more about Intel\u2019s innovations, go to <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=https%3A%2F%2Fnewsroom.intel.com%2F&amp;esheet=53412912&amp;newsitemid=20230605005191&amp;lan=en-US&amp;anchor=newsroom.intel.com&amp;index=3&amp;md5=867210411f5433f16407a67de45f4adf\">newsroom.intel.com<\/a> and <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fintel.com%2F&amp;esheet=53412912&amp;newsitemid=20230605005191&amp;lan=en-US&amp;anchor=intel.com&amp;index=4&amp;md5=8649645fb1ef10dae2a52b00e57ce46b\">intel.com<\/a>.<\/p>\n<p>\n\u00a9 Intel Corporation. Intel, the Intel logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.<\/p>\n<p><img decoding=\"async\" alt=\"\" src=\"https:\/\/cts.businesswire.com\/ct\/CT?id=bwnews&amp;sty=20230605005191r1&amp;sid=flmnd&amp;distro=nx&amp;lang=en\" style=\"width:0;height:0\" \/><span class=\"bwct31415\" \/><\/p>\n<p id=\"mmgallerylink\"><span id=\"mmgallerylink-phrase\">View source version on businesswire.com: <\/span><span id=\"mmgallerylink-link\"><a href=\"https:\/\/www.businesswire.com\/news\/home\/20230605005191\/en\/\" rel=\"nofollow\">https:\/\/www.businesswire.com\/news\/home\/20230605005191\/en\/<\/a><\/span><\/p>\n<p>\nRobin Holt<br \/>\n<br \/>1-503-616-1532<br \/>\n<br \/><a rel=\"nofollow\" href=\"mailto:robin.holt@intel.com\">robin.holt@intel.com<\/a><\/p>\n<p><b>KEYWORDS:<\/b> United States Japan North America Asia Pacific California<\/p>\n<p><b>INDUSTRY KEYWORDS:<\/b> Semiconductor Hardware Manufacturing Technology Engineering<\/p>\n<p><b>MEDIA:<\/b><\/p>\n<table cellpadding=\"3\" cellspacing=\"3\">\n<tr>\n<td><font face=\"Arial\" size=\"2\"><b>Logo<\/b><\/font><\/td>\n<\/tr>\n<tr>\n<td><img decoding=\"async\" src=\"https:\/\/mms.businesswire.com\/media\/20230605005191\/en\/817781\/3\/intel_logo.jpg\" alt=\"Logo\" \/><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\"><\/font><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\"><b>Photo<\/b><\/font><\/td>\n<\/tr>\n<tr>\n<td><img decoding=\"async\" src=\"https:\/\/mms.businesswire.com\/media\/20230605005191\/en\/1810038\/3\/Intel-Power-Via-Test-chips-1.jpg\" alt=\"Photo\" \/><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\">\u200bA wafer holds Blue Sky Creek test chips. The production test helps Intel refine Intel\u2019s PowerVia backside power technology. Expected as part of the Intel 20A manufacturing node in 2024, PowerVia will be the industry\u2019s first implementation of backside power in silicon, solving decades of interconnect bottlenecks. (Credit: Intel Corporation)<\/font><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\"><b>Photo<\/b><\/font><\/td>\n<\/tr>\n<tr>\n<td><img decoding=\"async\" src=\"https:\/\/mms.businesswire.com\/media\/20230605005191\/en\/1810039\/3\/Intel-Power-Via-Test-chips-2.jpg\" alt=\"Photo\" \/><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\">\u200bA wafer holds Blue Sky Creek test chips. The production test helps Intel refine Intel\u2019s PowerVia backside power technology. Expected as part of the Intel 20A manufacturing node in 2024, PowerVia will be the industry\u2019s first implementation of backside power in silicon, solving decades of interconnect bottlenecks. (Credit: Intel Corporation)<\/font><\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"<p>PowerVia Test Shows Industry-Leading Performance Intel is first to implement backside power in a product-like chip, resulting in over 90% cell utilization and other gains SANTA CLARA, Calif.&#8211;(BUSINESS WIRE)&#8211;What\u2019s New: Intel is the first in the industry to implement backside power delivery on a product-like test chip, achieving the performance needed to propel the world into the next era of computing. PowerVia, which will be introduced on the Intel 20A process node in the first half of 2024, is Intel\u2019s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer. This press release features multimedia. View the full release here: https:\/\/www.businesswire.com\/news\/home\/20230605005191\/en\/ \u200bA wafer holds &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/www.marketnewsdesk.com\/index.php\/powervia-test-shows-industry-leading-performance\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;PowerVia Test Shows Industry-Leading Performance&#8221;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-761592","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>PowerVia Test Shows Industry-Leading Performance - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/powervia-test-shows-industry-leading-performance\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"PowerVia Test Shows Industry-Leading Performance - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"PowerVia Test Shows Industry-Leading Performance Intel is first to implement backside power in a product-like chip, resulting in over 90% cell utilization and other gains SANTA CLARA, Calif.&#8211;(BUSINESS WIRE)&#8211;What\u2019s New: Intel is the first in the industry to implement backside power delivery on a product-like test chip, achieving the performance needed to propel the world into the next era of computing. PowerVia, which will be introduced on the Intel 20A process node in the first half of 2024, is Intel\u2019s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer. This press release features multimedia. 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PowerVia, which will be introduced on the Intel 20A process node in the first half of 2024, is Intel\u2019s industry-leading backside power delivery solution. It solves the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer. This press release features multimedia. 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