{"id":750373,"date":"2023-04-24T10:48:09","date_gmt":"2023-04-24T14:48:09","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-tapes-out-16g-ucie-advanced-package-ip-on-tsmcs-n3e-process-technology\/"},"modified":"2023-04-24T10:48:09","modified_gmt":"2023-04-24T14:48:09","slug":"cadence-tapes-out-16g-ucie-advanced-package-ip-on-tsmcs-n3e-process-technology","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-tapes-out-16g-ucie-advanced-package-ip-on-tsmcs-n3e-process-technology\/","title":{"rendered":"Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology"},"content":{"rendered":"<p>        <!--.bwalignc { text-align: center; list-style-position: inside }\n.bwlistdisc { list-style-type: disc }body {font:normal small Arial,Helvetica,sans-serif;color:#000;background-color:#fff;padding:24px;margin:0;} a img {border:0;} h3 {font-size:medium;color:#000;margin:0 0 1em 0; text-align:center;}-->  <\/p>\n<p class=\"bwalignc\"><b>Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology<\/b><\/p>\n<p class=\"bwalignc\"><i>Complete high-performance 2.5D package solution enables heterogeneous integration<\/i><\/p>\n<p>SAN JOSE, Calif.&#8211;(<a href=\"http:\/\/www.businesswire.com\">BUSINESS WIRE<\/a>)&#8211;<br \/>\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence<sup>\u00ae<\/sup> 16G UCIe\u2122 2.5D advanced package IP on TSMC\u2019s 3nm (N3E) process technology. Implemented on TSMC\u2019s 3DFabric\u2122 CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence\/machine learning (AI\/ML), mobile, automotive, storage and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets.<\/p>\n<p>\nCadence is currently engaged with a pipeline of Tier 1 customers, and UCIe advanced package IP collateral from the N3E test chip tapeout is shipping and available. The pre-verified solution can save customers time and effort through rapid integration.<\/p>\n<p>\nThe heterogeneous integration of Cadence\u2019s UCIe PHY and controller eases chiplet solutions with die reusability. The complete solution includes the following, which can be delivered with a complement of Cadence Verification IP (VIP) and TLM models:<\/p>\n<ul class=\"bwlistdisc\">\n<li><b>UCIe Advanced Package PHY: <\/b>Designed for a bump pitch that enables greater than 5Tbps\/mm of die edge bandwidth density, the UCIe advanced package PHY offers options that allow greater throughput performance while significantly improving power efficiency. It is flexible for integration on multiple types of 2.5D advanced packages, such as silicon interposer, silicon bridge, RDL and fanout-based packaging.\n<\/li>\n<li><b>UCIe Standard-Package PHY: <\/b>Options allow customers to reduce costs while maintaining high bandwidth and power efficiency. Cadence\u2019s circuit design allows customers to design down to the lower limits of the standard\u2019s bump pitch range to allow maximum BW\/mm while also enabling longer reach.\n<\/li>\n<li><b>UCIe Controller: <\/b>A soft IP that can be synthesized for multiple technology nodes, the UCIe controller is offered in a variety of options for different target applications and enables streaming, PCI Express<sup>\u00ae<\/sup> (PCIe<sup>\u00ae<\/sup>), and CXL protocols.\n<\/li>\n<\/ul>\n<p>\n\u201cThe UCIe Consortium supports companies designing chiplets for use in standard and advanced packaging. We are thrilled to extend our congratulations to Cadence on reaching the tape out milestone for the advanced package test chip which uses the die-to-die interconnect based on the UCIe 1.0 specification,\u201d said Dr. Debendra Das Sharma, chairman at the UCIe Consortium. \u201cMember company advancements in IP (scaling) and VIP (testing) are important components in the ecosystem. When paired with participation in UCIe work groups the industry will continue to see new chiplet based designs entering the market that are based on open industry standards that foster interoperability, compatibility, and innovation.\u201d<\/p>\n<p>\n\u201cCadence has been an industry pioneer in chiplet system solution offerings and continues to push the envelope of performance and power efficiency for a wide range of multi-chiplet applications in advanced nodes and packaging architectures,\u201d said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. \u201cWe see great value in aligning interconnect standards across the industry, and UCIe IP serves as a bridge, enabling open chiplet solutions for large SoCs reaching or exceeding the maximum reticle limit for manufacturing. The recent UCIe advanced package tapeout on the TSMC N3E process is a key milestone and commitment toward enabling customers with an open chiplet connectivity standard.\u201d<\/p>\n<p>\nThe Cadence 16G UCIe\u2122 2.5D advanced package IP supports Cadence\u2019s Intelligent System Design\u2122 strategy, which enables SoC design excellence. For more information, please visit: <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fwww.cadence.com%2Fgo%2F16gucie&amp;esheet=53382860&amp;newsitemid=20230420005022&amp;lan=en-US&amp;anchor=www.cadence.com%2Fgo%2Fucie16g&amp;index=1&amp;md5=6121fb192c2a04e3e592fc744a4791c8\">www.cadence.com\/go\/ucie16g<\/a>.<\/p>\n<p><b>About Cadence<\/b><\/p>\n<p>\nCadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world\u2019s most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at <a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fwww.cadence.com&amp;esheet=53382860&amp;newsitemid=20230420005022&amp;lan=en-US&amp;anchor=www.cadence.com&amp;index=2&amp;md5=a98c2dd1ec7f50417af6fc683fe797e1\">www.cadence.com<\/a>.<\/p>\n<p><i>\u00a9 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at <\/i><a rel=\"nofollow\" href=\"https:\/\/cts.businesswire.com\/ct\/CT?id=smartlink&amp;url=http%3A%2F%2Fwww.cadence.com%2Fgo%2Ftrademarks&amp;esheet=53382860&amp;newsitemid=20230420005022&amp;lan=en-US&amp;anchor=www.cadence.com%2Fgo%2Ftrademarks&amp;index=3&amp;md5=94eddf4d95d484abf102a600fbe96c72\"><i>www.cadence.com\/go\/trademarks<\/i><\/a><i> are trademarks or registered trademarks of Cadence Design Systems, Inc. <\/i><i>UCIe Consortium, Universal Chiplet Interconnect Express, and UCIe are trademarks of the UCIe Consortium. PCI Express and PCIe are registered trademarks or trademarks of PCI-SIG. SystemC is a trademark of Accellera Systems Initiative Inc. <\/i><i>All other trademarks are the property of their respective owners<\/i><i>.<\/i><\/p>\n<p>\nCategory: Featured<\/p>\n<p><img decoding=\"async\" alt=\"\" src=\"https:\/\/cts.businesswire.com\/ct\/CT?id=bwnews&amp;sty=20230420005022r1&amp;sid=flmnd&amp;distro=nx&amp;lang=en\" style=\"width:0;height:0\" \/><span class=\"bwct31415\" \/><\/p>\n<p id=\"mmgallerylink\"><span id=\"mmgallerylink-phrase\">View source version on businesswire.com: <\/span><span id=\"mmgallerylink-link\"><a href=\"https:\/\/www.businesswire.com\/news\/home\/20230420005022\/en\/\" rel=\"nofollow\">https:\/\/www.businesswire.com\/news\/home\/20230420005022\/en\/<\/a><\/span><\/p>\n<p>\nCadence Newsroom<br \/>\n<br \/>408-944-7039<br \/>\n<br \/><a rel=\"nofollow\" href=\"mailto:newsroom@cadence.com\">newsroom@cadence.com<\/a><\/p>\n<p><b>KEYWORDS:<\/b> California United States North America<\/p>\n<p><b>INDUSTRY KEYWORDS:<\/b> Internet Hardware Consumer Electronics Technology Software<\/p>\n<p><b>MEDIA:<\/b><\/p>\n<table cellpadding=\"3\" cellspacing=\"3\">\n<tr>\n<td><font face=\"Arial\" size=\"2\"><b>Logo<\/b><\/font><\/td>\n<\/tr>\n<tr>\n<td><img decoding=\"async\" src=\"https:\/\/mms.businesswire.com\/media\/20230420005022\/en\/633339\/3\/Cadence_Logo_2_Reg_Black.jpg\" alt=\"Logo\" \/><\/td>\n<\/tr>\n<tr>\n<td><font face=\"Arial\" size=\"2\"><\/font><\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology Complete high-performance 2.5D package solution enables heterogeneous integration SAN JOSE, Calif.&#8211;(BUSINESS WIRE)&#8211; Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence\u00ae 16G UCIe\u2122 2.5D advanced package IP on TSMC\u2019s 3nm (N3E) process technology. Implemented on TSMC\u2019s 3DFabric\u2122 CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence\/machine learning (AI\/ML), mobile, automotive, storage and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets. Cadence &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-tapes-out-16g-ucie-advanced-package-ip-on-tsmcs-n3e-process-technology\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology&#8221;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-750373","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-tapes-out-16g-ucie-advanced-package-ip-on-tsmcs-n3e-process-technology\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC\u2019s N3E Process Technology Complete high-performance 2.5D package solution enables heterogeneous integration SAN JOSE, Calif.&#8211;(BUSINESS WIRE)&#8211; Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence\u00ae 16G UCIe\u2122 2.5D advanced package IP on TSMC\u2019s 3nm (N3E) process technology. Implemented on TSMC\u2019s 3DFabric\u2122 CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence\/machine learning (AI\/ML), mobile, automotive, storage and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets. 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(Nasdaq: CDNS) today announced the tapeout of Cadence\u00ae 16G UCIe\u2122 2.5D advanced package IP on TSMC\u2019s 3nm (N3E) process technology. Implemented on TSMC\u2019s 3DFabric\u2122 CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence\/machine learning (AI\/ML), mobile, automotive, storage and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets. 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