{"id":528626,"date":"2021-08-16T17:03:12","date_gmt":"2021-08-16T21:03:12","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/rambus-advances-ai-ml-performance-with-8-4-gbps-hbm3-ready-memory-subsystem\/"},"modified":"2021-08-16T17:03:12","modified_gmt":"2021-08-16T21:03:12","slug":"rambus-advances-ai-ml-performance-with-8-4-gbps-hbm3-ready-memory-subsystem","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/rambus-advances-ai-ml-performance-with-8-4-gbps-hbm3-ready-memory-subsystem\/","title":{"rendered":"Rambus Advances AI\/ML Performance with 8.4 Gbps HBM3-Ready Memory Subsystem"},"content":{"rendered":"
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Highlights:<\/h2>\n

– Provides HBM3-ready memory subsystem solution consisting of fully-integrated PHY and digital controller<\/h2>\n

– Supports data rates up to 8.4 Gigabits per second (Gbps), enabling terabyte-scale bandwidth accelerators for artificial intelligence\/machine learning (AI\/ML) and high-performance computing (HPC) applications<\/h2>\n

– Leverages market-leading HBM2\/2E experience and installed-base to speed implementation of customer designs using next-generation HBM3 memory<\/h2>\n

PR Newswire<\/p>\n<\/p><\/div>\n

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\n SAN JOSE, Calif.<\/span>, Aug. 16, 2021<\/span> \/PRNewswire\/ — Rambus Inc.<\/a><\/u>\u00a0(NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the Rambus HBM3-ready memory interface subsystem consisting of a fully-integrated PHY<\/a>\u00a0and digital controller<\/a>. Supporting breakthrough data rates of up to 8.4 Gbps, the solution can deliver over a terabyte per second of bandwidth, more than double that of high-end HBM2E memory subsystems. With a market-leading position in HBM2\/2E memory interface deployments, Rambus is ideally suited to enable customers’ implementations of accelerators using next-generation HBM3 memory. <\/p>\n

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“The memory bandwidth requirements of AI\/ML training are insatiable with leading-edge training models now surpassing billions of parameters,” said Soo Kyoum Kim<\/span>, associate vice president, Memory Semiconductors at IDC. “The Rambus HBM3-ready memory subsystem raises the bar for performance enabling state-of-the-art AI\/ML and HPC applications.” <\/p>\n

Rambus achieves HBM3 operation of up to 8.4 Gbps leveraging over 30 years of high-speed signaling expertise, and a strong history of 2.5D memory system architecture design and enablement. In addition to the fully-integrated HBM3-ready memory subsystem, Rambus provides its customers with interposer and package reference designs to speed their products to market.<\/p>\n

“With the performance achieved by our HBM3-ready memory subsystem, designers can deliver the bandwidth needed by the most demanding designs,” said Matt Jones<\/span>, general manager of Interface IP at Rambus. “Our fully-integrated PHY and digital controller solution builds on our broad installed base of HBM2 customer deployments and is backed by a full suite of support services to ensure first-time right implementations for mission-critical AI\/ML designs.” <\/p>\n

\n Benefits of the Rambus HBM3-ready Memory Interface Subsystem:<\/b>\n <\/p>\n