{"id":500561,"date":"2021-06-03T09:26:44","date_gmt":"2021-06-03T13:26:44","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/synopsys-expands-multi-die-solution-leadership-with-industrys-lowest-latency-die-to-die-controller-ip\/"},"modified":"2021-06-03T09:26:44","modified_gmt":"2021-06-03T13:26:44","slug":"synopsys-expands-multi-die-solution-leadership-with-industrys-lowest-latency-die-to-die-controller-ip","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/synopsys-expands-multi-die-solution-leadership-with-industrys-lowest-latency-die-to-die-controller-ip\/","title":{"rendered":"Synopsys Expands Multi-Die Solution Leadership with Industry&#8217;s Lowest Latency Die-to-Die Controller IP"},"content":{"rendered":"<div class=\"xn-newslines\">\n<h2 class=\"xn-hedline\">Complete DesignWare Die-to-Die Controller and PHY IP Solution Maximizes Performance for Efficient Inter-Die Connectivity in High-Performance Computing, AI and Networking SoCs<\/h2>\n<p class=\"xn-distributor\">PR Newswire<\/p>\n<\/p><\/div>\n<div class=\"xn-content\">\n<p>\n        <span class=\"xn-location\">MOUNTAIN VIEW, Calif.<\/span>, <span class=\"xn-chron\">June 3, 2021<\/span> \/PRNewswire\/ &#8212;<\/p>\n<p>\n        <b>Highlights of this Announcement:<\/b>\n      <\/p>\n<ul type=\"disc\">\n<li>The complete DesignWare Die-to-Die IP solution, including controller, 112G USR\/XSR and HBI PHYs, supports die splitting and compute scaling <\/li>\n<li>New Die-to-Die Controller&#8217;s error correction mechanisms with replay and optional forward error correction minimize bit error rate for reliable die-to-die links <\/li>\n<li>Low-latency architecture supports AMBA CXS for efficient interface with Arm\u00ae Neoverse\u2122 Coherent Mesh Network <\/li>\n<li>Synopsys provides a complete multi-die solution with Die-to-Die IP, HBM IP and 3DIC Compiler for system-in-package integration \u00a0\u00a0<\/li>\n<\/ul>\n<p>\n        <a target=\"_blank\" href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3184036-1&amp;h=739756899&amp;u=https%3A%2F%2Fwww.synopsys.com%2F&amp;a=Synopsys%2C+Inc.\" rel=\"nofollow noopener\">Synopsys, Inc.<\/a>\u00a0(Nasdaq:\u00a0<a target=\"_blank\" href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3184036-1&amp;h=2287481419&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fcompany%2Finvestor-relations.html&amp;a=SNPS\" rel=\"nofollow noopener\">SNPS<\/a>) today announced its new <a target=\"_blank\" href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3184036-1&amp;h=1766261012&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdw%2Fipdir.php%3Fds%3Ddwc_die-to-die_controller&amp;a=DesignWare%C2%AE+Die-to-Die+Controller+IP\" rel=\"nofollow noopener\">DesignWare\u00ae Die-to-Die Controller IP<\/a>, which complements the company&#8217;s existing 112G USR\/XSR PHY IP for a complete die-to-die IP solution. With the complete IP solution, designers benefit from a low-latency, high-bandwidth die-to-die connectivity offering that addresses the increased workload and faster data movement demands of high-performance computing, artificial intelligence (AI) and networking SoCs. The DesignWare Die-to-Die Controller and <span class=\"xn-person\">PHY IP<\/span> are part of the Synopsys multi-die solution, consisting of HBM IP and 3DIC Compiler, accelerating SoC designs requiring advanced packaging. <\/p>\n<p>&#8220;Interconnect technology is increasingly vital for the next-generation of performant, customized infrastructure SoCs,&#8221; said <span class=\"xn-person\">Jeff Defilippi<\/span>, director of product management, Infrastructure Line of Business, Arm. &#8220;With its low-latency, native support for AMBA CXS, Synopsys DesignWare Die-to-Die Controller can easily integrate with the Arm Coherent Mesh Network to provide our mutual customers access to the multichip IP solutions offering new scale-up performance and composability options required for this next era of infrastructure compute.&#8221;<\/p>\n<p>The DesignWare Die-to-Die Controller provides error recovery mechanisms such as optional forward-error correction and cyclic redundancy check for higher data integrity and link reliability. The DesignWare Die-to-Die controller&#8217;s flexible configuration supporting the AMBA\u00ae CXS and AXI protocols allows coherent and non-coherent data communication for easy integration into Arm-based and other high-performance SoCs. The DesignWare Die-to-Die Controller with support for up to 1.8Tb\/s PHY bandwidth addresses high-performance computing demands of SoCs requiring robust die-to-die connectivity. <\/p>\n<p>&#8220;The trend of die splitting and disaggregation require ultra- and extra-short reach links to enable inter-die connectivity with high data rates,&#8221; said <span class=\"xn-person\">John Koeter<\/span>, senior vice president of marketing and strategy for IP at Synopsys. &#8220;Our complete DesignWare Die-to-Die IP solution offers ultra-low-latency controller and high-performance PHYs that have been adopted by multiple customers, allowing designers to integrate high-quality IP in their multi-die SoCs with confidence while minimizing integration risk.&#8221;<\/p>\n<p>\n        <span>Synopsys&#8217; broad DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys&#8217; IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Our extensive investment in IP quality and comprehensive technical support enable designers to reduce integration risk and accelerate time-to-market. For more information, please visit <\/span><br \/>\n        <span><br \/>\n          <a target=\"_blank\" href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3184036-1&amp;h=1127734991&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware&amp;a=https%3A%2F%2Fwww.synopsys.com%2Fdesignware\" rel=\"nofollow noopener\"><br \/>\n            <span>https:\/\/www.synopsys.com\/designware<\/span><br \/>\n          <\/a><br \/>\n        <\/span><br \/>\n        <span>.<\/span>\n      <\/p>\n<p>\n        <b>Availability and Resources<\/b>\n      <\/p>\n<p>The DesignWare Die-to-Die Controller IP is available now to early adopters. The Synopsys DesignWare Die-to-Die USR\/XSR PHY IP in 12nm, 7nm and 5nm processes are available now with a roadmap to 3nm. The HBI PHY IP in 7nm and 5nm processes are available now. <\/p>\n<p>For more information, visit the <a target=\"_blank\" href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3184036-1&amp;h=1301847835&amp;u=https%3A%2F%2Fwww.synopsys.com%2Fdesignware-ip%2Finterface-ip%2Fdie-to-die.html&amp;a=DesignWare+Die-to-Die+IP\" rel=\"nofollow noopener\">DesignWare Die-to-Die IP<\/a> page. <\/p>\n<p>\n        <b>About Synopsys<\/b>\n      <\/p>\n<p>Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software\u2122 partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&amp;P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry&#8217;s broadest portfolio of application security testing tools and services. Whether you&#8217;re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at <a target=\"_blank\" href=\"https:\/\/c212.net\/c\/link\/?t=0&amp;l=en&amp;o=3184036-1&amp;h=2058327734&amp;u=http%3A%2F%2Fwww.synopsys.com%2F&amp;a=www.synopsys.com\" rel=\"nofollow noopener\">www.synopsys.com<\/a>. <\/p>\n<p>\n        <b>Editorial Contact: <br \/><\/b><br \/>\n        <span class=\"xn-person\">Simone Souza<\/span><br \/>\n        <br \/>Synopsys, Inc.<br \/>650-584-6454<br \/><a target=\"_blank\" href=\"mailto:simone@synopsys.com\" rel=\"nofollow noopener\">simone@synopsys.com<\/a><\/p>\n<p id=\"PURL\">\n        <img loading=\"lazy\" decoding=\"async\" title=\"Cision\" width=\"12\" height=\"12\" alt=\"Cision\" src=\"https:\/\/c212.net\/c\/img\/favicon.png?sn=SF98543&amp;sd=2021-06-03\" \/> View original content:<a id=\"PRNURL\" rel=\"nofollow\" href=\"http:\/\/www.prnewswire.com\/news-releases\/synopsys-expands-multi-die-solution-leadership-with-industrys-lowest-latency-die-to-die-controller-ip-301305228.html\">http:\/\/www.prnewswire.com\/news-releases\/synopsys-expands-multi-die-solution-leadership-with-industrys-lowest-latency-die-to-die-controller-ip-301305228.html<\/a><\/p>\n<p>SOURCE  Synopsys, Inc.<\/p>\n<\/p><\/div>\n<p>    <img decoding=\"async\" alt=\"\" src=\"https:\/\/rt.prnewswire.com\/rt.gif?NewsItemId=SF98543&amp;Transmission_Id=202106030905PR_NEWS_USPR_____SF98543&amp;DateId=20210603\" style=\"border:0px;width:1px;height:1px\" \/><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Complete DesignWare Die-to-Die Controller and PHY IP Solution Maximizes Performance for Efficient Inter-Die Connectivity in High-Performance Computing, AI and Networking SoCs PR Newswire MOUNTAIN VIEW, Calif., June 3, 2021 \/PRNewswire\/ &#8212; Highlights of this Announcement: The complete DesignWare Die-to-Die IP solution, including controller, 112G USR\/XSR and HBI PHYs, supports die splitting and compute scaling New Die-to-Die Controller&#8217;s error correction mechanisms with replay and optional forward error correction minimize bit error rate for reliable die-to-die links Low-latency architecture supports AMBA CXS for efficient interface with Arm\u00ae Neoverse\u2122 Coherent Mesh Network Synopsys provides a complete multi-die solution with Die-to-Die IP, HBM IP and 3DIC Compiler for system-in-package integration \u00a0\u00a0 Synopsys, Inc.\u00a0(Nasdaq:\u00a0SNPS) today announced its new DesignWare\u00ae Die-to-Die Controller IP, which complements the &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/www.marketnewsdesk.com\/index.php\/synopsys-expands-multi-die-solution-leadership-with-industrys-lowest-latency-die-to-die-controller-ip\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Synopsys Expands Multi-Die Solution Leadership with Industry&#8217;s Lowest Latency Die-to-Die Controller IP&#8221;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-500561","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - 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