{"id":482213,"date":"2021-04-27T08:03:48","date_gmt":"2021-04-27T12:03:48","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/renesas-expands-femtoclock-timing-portfolio-for-high-performance-communications-and-data-center-applications\/"},"modified":"2021-04-27T08:03:48","modified_gmt":"2021-04-27T12:03:48","slug":"renesas-expands-femtoclock-timing-portfolio-for-high-performance-communications-and-data-center-applications","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/renesas-expands-femtoclock-timing-portfolio-for-high-performance-communications-and-data-center-applications\/","title":{"rendered":"Renesas Expands FemtoClock Timing Portfolio for High-Performance Communications and Data Center Applications"},"content":{"rendered":"

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Renesas Expands FemtoClock Timing Portfolio for High-Performance Communications and Data Center Applications<\/b><\/p>\n

FemtoClock2 Family Simplifies Design with Industry\u2019s Lowest Power and Smallest 75fs Jitter Clocks<\/i><\/p>\n

TOKYO–(BUSINESS WIRE<\/a>)–
\nRenesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today expanded its timing solutions portfolio with a new sub-100fs point-of-use clock solution for data center, server, and network infrastructure markets. The new FemtoClock2 family includes ultra-low jitter clock generators and jitter attenuators in a small 4×4 mm2<\/sup> package, enabling cost-effective and simple clock tree implementation for next-generation, high-speed interconnect designs.\n<\/p>\n

This press release features multimedia. View the full release here: https:\/\/www.businesswire.com\/news\/home\/20210427005260\/en\/<\/a><\/p>\n

\"Smallest,<\/p>\n

Smallest, lowest power 75fs jitter clocks simplify design (Graphic: Business Wire)<\/p>\n<\/div>\n

\nFeaturing best-in-class jitter as low as 64fs RMS, FemtoClock2 enables customers to easily meet next-generation PAM4 requirements on new switch or router designs. With a 4×4 mm2<\/sup> form factor, the FemtoClock2 family<\/a> is less than one third the size of similar solutions on the market. This allows designers to place the clock source at the point of use \u2013 very close to the device receiving the clock signal \u2013 for streamlined PCB layout design, reduced cross talk, and cleaner signals. Flexibility makes the family useful in many applications. FemtoClock2 can be configured as a DCO, clock generator, or jitter attenuator, offering valuable design flexibility and reuse.\n<\/p>\n

\n\u201cPAM4 technology is enabling a major leap in data transmission rates in both communications and data center segments resulting in stringent requirement on the clock in such systems,\u201d said Bobby Matinpour, Vice President of Timing Products, Data Center Business Division at Renesas. \u201cExpanding our popular FemtoClock lineup, Renesas offers a new high-performance family that delivers superior jitter performance with low power in a small form factor, enabling placement of the clock anywhere on the board at the point of use. This greatly simplifies the design by eliminating the additive jitter associated with the extensive clock routing on the board.\u201d\n<\/p>\n

Key Features of the FemtoClock2 Family <\/b><\/p>\n