{"id":401103,"date":"2020-12-16T10:48:32","date_gmt":"2020-12-16T15:48:32","guid":{"rendered":"http:\/\/www.marketnewsdesk.com\/?p=401103"},"modified":"2020-12-16T10:48:32","modified_gmt":"2020-12-16T15:48:32","slug":"samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\/","title":{"rendered":"Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs"},"content":{"rendered":"

<\/p>\n

Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs<\/b><\/p>\n

Proven flow featuring the Celsius Thermal Solver and Clarity 3D Solver accelerates 2.5\/3D designs for hyperscale, communications and automotive applications <\/i><\/p>\n

SAN JOSE, Calif.–(BUSINESS WIRE<\/a>)–
\nCadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry has certified the complete Cadence\u00ae<\/sup> system analysis and advanced packaging design tool flow as a Samsung Multi-Die Integration (MDI\u2122<\/sup>) advanced packaging reference flow. This proven on-\/off-chip design flow, which features Cadence multi-physics system analysis tools including the Celsius\u2122<\/sup> Thermal Solver and Clarity\u2122<\/sup> 3D Solver, accelerates the planning, implementation, verification and signoff of 2.5D and 3D multi-die chip designs employed in hyperscale computing, 5G communications and automotive applications, particularly those utilizing artificial intelligence (AI). For more information, visit www.cadence.com\/go\/samsungadvpkg<\/a>.\n<\/p>\n

\nDesigners of advanced IC packages face many challenges that are directly addressed by this documented, step-by-step approach to validate critical electrical and thermal requirements for first-pass success. Cadence collaborated with Samsung to certify the flow, which was verified on eight SerDes differential pairs across a 46mm x 32mm interposer.\n<\/p>\n

\nCadence\u2019s multi-physics system analysis solution includes the Celsius Thermal Solver, Clarity 3D Solver, Voltus\u2122<\/sup> IC Power Integrity Solution, Sigrity SystemSI\u2122<\/sup> technology and Sigrity\u2122<\/sup> Broadband SPICE\u00ae<\/sup> technology, which can be used with the Allegro\u00ae<\/sup> Package Designer Plus for ball-grid array (BGA) substrate layout and analysis and with the Innovus\u2122<\/sup> Implementation System for layout and analysis of 3D-IC chip stacks. Both implementation solutions integrate seamlessly with Cadence\u2019s OrbitIO\u2122<\/sup> Interconnect Designer for system-level planning and optimization, as well as the Pegasus\u2122<\/sup> Verification System for signoff design rule checks (DRCs) and layout versus schematic (LVS).\n<\/p>\n

\nUsing the Clarity 3D Solver, the SerDes connections were extracted with all surrounding power and the complex package with a level of detail that was not possible with other commercially available 3D advanced packaging solutions. The SI and EM analyses were performed by the Sigrity SystemSI technology and the Clarity 3D Solver respectively. The Celsius Thermal Solver directly read the extracted complex package design and generated the thermal model that was used in the simulation. The thermal solution was enabled by the direct read of the chip-level GDS database and contained more detail than other commercially available thermal tools, with highly accurate results.\n<\/p>\n

\n\u201cThe results from the Cadence analysis tools, particularly the Celsius Thermal Solver and Clarity 3D Solver, provide pure 3D full-wave and highly detailed thermal simulation for much more accurate results,\u201d said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. \u201cThis collaboration provides our mutual customers with a trusted system design enablement solution for advanced packages that enables them to implement state-of-the-art products.\u201d\n<\/p>\n

\n\u201cThis certification helps our mutual customers quickly achieve lower power and higher performance using a much smaller form factor in their designs,\u201d stated Ben Gu, vice president of multi-physics system analysis in the Custom IC & PCB Group at Cadence. \u201cExtraction accuracy is greatly improved over previous disjointed approaches from multiple EDA vendors. This flow helps reduce cost and improve reliability of their products using advanced MDI packaging techniques.\u201d\n<\/p>\n

\nThe certified Cadence flow supports Cadence\u2019s Intelligent System Design\u2122<\/sup> strategy, which enables customers to accelerate system innovation.\n<\/p>\n

About Cadence <\/b><\/p>\n

\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world\u2019s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com<\/a>.\n<\/p>\n

\u00a9 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com\/go\/trademarks<\/a> are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.<\/i><\/p>\n

\"\"<\/p>\n

View source version on businesswire.com: <\/span>https:\/\/www.businesswire.com\/news\/home\/20201216005340\/en\/<\/a><\/span><\/p>\n

\nCadence Newsroom
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408-944-7039
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newsroom@cadence.com<\/a><\/p>\n

KEYWORDS:<\/b> California United States North America<\/p>\n

INDUSTRY KEYWORDS:<\/b> Software Networks Hardware Electronic Design Automation Data Management Technology Semiconductor Security<\/p>\n

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Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs Proven flow featuring the Celsius Thermal Solver and Clarity 3D Solver accelerates 2.5\/3D designs for hyperscale, communications and automotive applications SAN JOSE, Calif.–(BUSINESS WIRE)– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry has certified the complete Cadence\u00ae system analysis and advanced packaging design tool flow as a Samsung Multi-Die Integration (MDI\u2122) advanced packaging reference flow. This proven on-\/off-chip design flow, which features Cadence multi-physics system analysis tools including the Celsius\u2122 Thermal Solver and Clarity\u2122 3D Solver, accelerates the planning, implementation, verification and signoff of 2.5D and 3D multi-die chip designs employed in hyperscale computing, 5G communications and automotive applications, particularly those … <\/p>\n

Continue reading “Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-401103","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"\nSamsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs Proven flow featuring the Celsius Thermal Solver and Clarity 3D Solver accelerates 2.5\/3D designs for hyperscale, communications and automotive applications SAN JOSE, Calif.–(BUSINESS WIRE)– Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Samsung Foundry has certified the complete Cadence\u00ae system analysis and advanced packaging design tool flow as a Samsung Multi-Die Integration (MDI\u2122) advanced packaging reference flow. This proven on-\/off-chip design flow, which features Cadence multi-physics system analysis tools including the Celsius\u2122 Thermal Solver and Clarity\u2122 3D Solver, accelerates the planning, implementation, verification and signoff of 2.5D and 3D multi-die chip designs employed in hyperscale computing, 5G communications and automotive applications, particularly those … Continue reading "Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\/3D Chip Designs"\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.marketnewsdesk.com\/index.php\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\/\" \/>\n<meta property=\"og:site_name\" content=\"Market Newsdesk\" \/>\n<meta property=\"article:published_time\" content=\"2020-12-16T15:48:32+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/cts.businesswire.com\/ct\/CT?id=bwnews&sty=20201216005340r1&sid=flmnd&distro=nx&lang=en\" \/>\n<meta name=\"author\" content=\"Newsdesk\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Newsdesk\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\\\/\"},\"author\":{\"name\":\"Newsdesk\",\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/#\\\/schema\\\/person\\\/482f27a394d4fda80ecb5499e519d979\"},\"headline\":\"Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\\\/3D Chip Designs\",\"datePublished\":\"2020-12-16T15:48:32+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\\\/\"},\"wordCount\":737,\"image\":{\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/cts.businesswire.com\\\/ct\\\/CT?id=bwnews&sty=20201216005340r1&sid=flmnd&distro=nx&lang=en\",\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\\\/\",\"url\":\"https:\\\/\\\/www.marketnewsdesk.com\\\/index.php\\\/samsung-foundry-certifies-cadence-system-analysis-and-advanced-packaging-design-tool-flow-for-2-5-3d-chip-designs\\\/\",\"name\":\"Samsung Foundry Certifies Cadence System Analysis and Advanced Packaging Design Tool Flow for 2.5\\\/3D Chip Designs - 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