{"id":391934,"date":"2020-12-02T11:03:10","date_gmt":"2020-12-02T16:03:10","guid":{"rendered":"http:\/\/www.marketnewsdesk.com\/?p=391934"},"modified":"2020-12-02T11:03:10","modified_gmt":"2020-12-02T16:03:10","slug":"mobiveil-announces-compute-express-link-cxl-2-0-design-ip-successful-completion-of-cxl-1-1-validation-with-intels-cxl-host-platform","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/mobiveil-announces-compute-express-link-cxl-2-0-design-ip-successful-completion-of-cxl-1-1-validation-with-intels-cxl-host-platform\/","title":{"rendered":"Mobiveil Announces Compute Express Link (CXL) 2.0 Design IP, Successful Completion of CXL 1.1 Validation with Intel\u2019s CXL Host Platform"},"content":{"rendered":"

\nHighly Configurable, Low-Latency CXL Controller IP Supports Variety of High-Performance Applications
\n<\/h2>\n
\n

MILPITAS, Calif., Dec. 02, 2020 (GLOBE NEWSWIRE) — Mobiveil, Inc.<\/a>, a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced its Compute Express Link\u2122 (CXL) 2.0 Design IP and successful completion of CXL 1.1 validation with Intel\u2019s CXL host platform.\u00a0<\/p>\n

Mobiveil\u2019s CXL controller IP (COMPEX\u2122) is a highly configurable, low-latency CXL controller that supports host and device modes for several high-performance applications, such as data center accelerators, memory expanders, artificial intelligence\/machine learning and special applications.<\/p>\n

The COMPEX controller IP is designed for CXL 2.0 specification and supports host and type 1, type 2 and type 3 devices. COMPEX also supports dual mode where it can be configured to operate either as a host or any of the device types. <\/p>\n

COMPEX supports up to 16 lanes on a flex bus interface and is compliant with the PIPE 5.2 specification. It provides a simple packet-based interface-to-user logic that supports 128-bit, 256-bit and 512-bit data path widths and provides a low-latency path for easy integration into a customer ASIC. An implementation can choose one of the datapath widths based on the number of lanes and target technology to get low-latency and optimized power consumption from COMPEX controller. <\/p>\n

For CXL.io, COMPEX uses Mobiveil\u2019s PCI-SIG\u00ae compliant GPEX\u2122 controller and adds highly efficient and configurable CXL.mem and CXL.cache layers for a low-latency coherent path. The COMPEX controller IP version 1.1 recently completed system-level validation using future Intel Xeon Scalable processors codenamed Sapphire Rapids.<\/p>\n

\u201cFrom the moment we kicked off the CXL IP development, our IP engineering as well as our system engineering teams focused on delivering high-performance, high-quality IP validated in a system-level environment,\u201d comments Gopa Periyadan, Mobiveil\u2019s COO. \u201cWe worked closely with the Intel CXL validation team to make sure these goals were met. Before porting the COMPEX controller to Mobiveil\u2019s FPGA platform, it was fully verified for functionality and compliance using Avery Design Systems\u2019 CXL Verification IP. This newly validated IP will help our customers accelerate high-performance applications.\u201d<\/p>\n

\u201cWe are pleased to see CXL 1.1 Type 2 Device IP seamlessly interface with our Sapphire Rapids CPU using the CXL protocol and successfully execute data transfers on CXL.mem and CXL.cache paths,\u201d says Mahesh Wagh, Senior Principal Engineer in Intel\u2019s I\/O Technology and Standards Group. \u201cThe availability of Mobiveil\u2019s CXL IP will help accelerate the adoption of the CXL standard and the proliferation of CXL devices in the market.\u201d <\/p>\n

Mobiveil\u2019s controller has a simple, configurable and layered architecture independent of application logic, PHYs, implementation tools and, most important, the target technology itself. It allows the user to migrate between standard cell technologies and FPGAs. The controller\u2019s flexible backend interface can be integrated into a wide range of applications.<\/p>\n

The CXL controller architecture optimizes link utilization, latency, reliability, power consumption and silicon footprint. It handles PCI Express\u00ae ordering rules and implements multiple virtual circuits (VCs) and associated flow control logic in both directions. The packet-oriented user logic interface also supports PIPE 5-compliant PHYs, and flexible lane ordering and support for lane reversal.<\/p>\n

Mobiveil\u2019s IP team has more than 15 years of experience developing IP blocks for several high-speed serial interconnect solutions. The interface IP designed by Mobiveil is integrated in hundreds of system-on-chip (SoC) designs and shipped in millions of devices.

Availability
<\/strong>
Mobiveil\u2019s CXL 1.1-based COMPEX Controller IP is available for licensing now. It can be targeted to FPGA, eASIC and Structured ASIC technologies. The CXL 2.0-based COMPEX controller will be available in Q1 2021.<\/p>\n

Pricing is available on request.<\/p>\n

More information on Mobiveil\u2019s COMPEX IP is found at the Mobiveil website<\/a> or email at ip@mobiveil.com<\/a>. \u00a0

About Mobiveil, Inc<\/strong>.<\/p>\n

Mobiveil<\/a>\u00a0is a fast\u2010growing technology company that specializes in development of Silicon Intellectual Property (SIP), platforms and solutions for networking, storage and enterprise markets. The Mobiveil team leverages decades of experience to deliver high\u2010quality, production\u2010proven, high-speed serial interconnect SIP cores, and custom and standard form factor hardware boards to leading companies worldwide. With a highly motivated engineering team, dedicated integration support, a flexible business model, strong industry presence through strategic alliances and key partnerships, Mobiveil solutions add value to users by matching their product goals on time and within budget. Mobiveil is headquartered in Silicon Valley with engineering development centers located in Milpitas, Calif., Chennai, Bangalore and Hyderabad, India, and sales offices and representatives located in the U.S., Europe, Israel, Japan, Taiwan and the People\u2019s Republic of China.

Engage with Mobiveil at:
<\/strong>
Website: www.mobiveil.com<\/a>
Twitter: @Mobiveil
LinkedIn: https:\/\/www.linkedin.com\/company-beta\/2725746\/<\/a>
Facebook: https:\/\/www.facebook.com\/Mobiveil<\/a>\u00a0\u00a0<\/p>\n

\n GPEX and COMPEX are trademarks of Mobiveil. Mobiveil acknowledges trademarks or registered trademarks of other organizations for their respective products and services<\/em>
\n
\n Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.<\/em>\n <\/p>\n

For more information, contact:
Nanette Collins
Public Relations for Mobiveil<\/a>
(617) 437-1822
nanette@nvc.com<\/a><\/p>\n<\/p>\n


\n
\n \n <\/div>\n

<\/div>\n","protected":false},"excerpt":{"rendered":"

Highly Configurable, Low-Latency CXL Controller IP Supports Variety of High-Performance Applications MILPITAS, Calif., Dec. 02, 2020 (GLOBE NEWSWIRE) — Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced its Compute Express Link\u2122 (CXL) 2.0 Design IP and successful completion of CXL 1.1 validation with Intel\u2019s CXL host platform.\u00a0 Mobiveil\u2019s CXL controller IP (COMPEX\u2122) is a highly configurable, low-latency CXL controller that supports host and device modes for several high-performance applications, such as data center accelerators, memory expanders, artificial intelligence\/machine learning and special applications. The COMPEX controller IP is designed for CXL 2.0 specification and supports host and type 1, type 2 and type 3 devices. COMPEX also supports dual mode where it … <\/p>\n

Continue reading “Mobiveil Announces Compute Express Link (CXL) 2.0 Design IP, Successful Completion of CXL 1.1 Validation with Intel\u2019s CXL Host Platform”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-391934","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"\nMobiveil Announces Compute Express Link (CXL) 2.0 Design IP, Successful Completion of CXL 1.1 Validation with Intel\u2019s CXL Host Platform - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/mobiveil-announces-compute-express-link-cxl-2-0-design-ip-successful-completion-of-cxl-1-1-validation-with-intels-cxl-host-platform\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Mobiveil Announces Compute Express Link (CXL) 2.0 Design IP, Successful Completion of CXL 1.1 Validation with Intel\u2019s CXL Host Platform - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Highly Configurable, Low-Latency CXL Controller IP Supports Variety of High-Performance Applications MILPITAS, Calif., Dec. 02, 2020 (GLOBE NEWSWIRE) — Mobiveil, Inc., a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, today announced its Compute Express Link\u2122 (CXL) 2.0 Design IP and successful completion of CXL 1.1 validation with Intel\u2019s CXL host platform.\u00a0 Mobiveil\u2019s CXL controller IP (COMPEX\u2122) is a highly configurable, low-latency CXL controller that supports host and device modes for several high-performance applications, such as data center accelerators, memory expanders, artificial intelligence\/machine learning and special applications. The COMPEX controller IP is designed for CXL 2.0 specification and supports host and type 1, type 2 and type 3 devices. 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