{"id":1009676,"date":"2026-10-13T11:34:50","date_gmt":"2026-10-13T15:34:50","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/ase-expands-powersip-platform-for-next-generation-ai-power-delivery\/"},"modified":"2026-10-13T11:34:50","modified_gmt":"2026-10-13T15:34:50","slug":"ase-expands-powersip-platform-for-next-generation-ai-power-delivery","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/ase-expands-powersip-platform-for-next-generation-ai-power-delivery\/","title":{"rendered":"ASE Expands PowerSiP\u2122 Platform for Next-Generation AI Power Delivery"},"content":{"rendered":"

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ASE Expands PowerSiP\u2122 Platform for Next-Generation AI Power Delivery<\/b><\/p>\n

Vertically integrated 3D SiP modules shorten high-current transmissions path, reducing parasitic routing losses by 50% or more to enhance system efficiency<\/i><\/p>\n

SUNNYVALE, Calif.–(BUSINESS WIRE<\/a>)–
\nAdvanced Semiconductor Engineering, Inc. (ASE), a member of ASE Technology Holding Co., Ltd. (NYSE: ASX, TAIEX: 3711) and a leading provider of semiconductor assembly and test services, today announced the expansion of its PowerSiP\u2122 platform with a 3D System-in-Package (SiP) solution designed to enable vertically integrated voltage regulator modules (VRMs) for higher system efficiency in AI data center and high-performance computing applications. Available now, the solution combines qualified assembly technologies and a sub-module toolbox to support miniaturized, highly integrated, and thin VRMs for vertical board-to-chip power delivery. By bringing voltage regulation closer to the processor, the vertical architecture can cut parasitic routing losses by 50% or more, helping improve overall system efficiency as AI compute power requirements continue to rise.<\/p>\n

\nAs AI processors continue to scale in performance, their energy requirements are increasing significantly, making efficient power delivery a critical system-level challenge. Today\u2019s high-performance AI SoCs can exceed kilowatt-level power and require peak currents greater than 1,000 amps at sub-volt levels. At these currents, traditional lateral architectures can introduce significant routing losses as electricity travels across the PCB, through package substrates and interconnects before reaching the processor. Reducing the distance between voltage regulation and the processor is therefore becoming increasingly important to minimize losses and improve overall system efficiency.<\/p>\n

\nASE\u2019s PowerSiP\u2122 vertical integration toolbox includes double-sided connected capacitors sandwiched between coreless substrates; substrate-less, solder-free cap array modules with exposed terminals for embedded substrate or PCB solutions; high-aspect-ratio 4:1 copper pin integration for lower packaging impedance; and high-density active and passive component integration using single- or double-sided molding. Together, these capabilities address the density and thickness constraints associated with placing voltage regulation on the back side of the PCB in space-constrained compute trays.<\/p>\n

\n\u201cPower efficiency is becoming a defining challenge for next-generation AI systems,\u201d said Dr. Harrison Chang, Vice President of Corporate Research and Development at ASE. \u201cBy shortening the high-current transmission path, our vertically integrated PowerSiP\u2122 solution can reduce parasitic routing losses by 50% or more, translating directly into meaningful power savings at the system level.\u201d<\/p>\n

\n\u201cAI systems are placing unprecedented demands on board-to-chip power delivery, making the final stage of voltage regulation increasingly important,\u201d said Dr. C. P. Hung, Vice President of Corporate Research and Development at ASE. \u201cPowerSiP\u2122 brings together advanced packaging and integration technologies that enable compact, high-density voltage regulation to be positioned directly beneath the processor, addressing the stringent space and performance requirements of next-generation AI systems.\u201d<\/p>\n

\n\u201cAs AI infrastructure evolves toward increasingly heterogeneous and modular compute architectures, system-level power efficiency will become even more critical. The expansion of PowerSiP\u2122 reflects ASE\u2019s focus on packaging innovation that addresses broader system-level power challenges,\u201d said Yin Chang, Executive Vice President at ASE. \u201cOur qualified assembly technologies provide customers with a flexible toolbox for building compact, highly integrated VRMs that can be vertically integrated for next-generation GPUs, TPUs and custom ASICs in AI data center and HPC applications.\u201d<\/p>\n

\nASE will participate at SEMICON West 2026 in San Francisco, from October 13 to October 15, where Executive Vice President Yin Chang will deliver the Advanced Packaging Heterogeneous Integration Summit keynote titled \u201cThe Architecture of Intelligence: Advanced Packaging for AI at Scale.\u201d Simultaneously, ASE will participate at OCP 2026 in San Jose, from October 13 to October 15, where Corporate Vice President Dr. CP Hung will participate on a panel in the Open Chiplet Economy session, discussing \u201cPhysical AI \u2013 Addressing the barriers to interoperable chiplets in automotive and robotics.\u201d<\/p>\n

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