{"id":1005090,"date":"2026-09-22T12:45:46","date_gmt":"2026-09-22T16:45:46","guid":{"rendered":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/"},"modified":"2026-09-22T12:45:46","modified_gmt":"2026-09-22T16:45:46","slug":"cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization","status":"publish","type":"post","link":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/","title":{"rendered":"Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization"},"content":{"rendered":"

<\/p>\n

Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization<\/b><\/p>\n

New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff<\/i>\u2011grade quality and performance, validated in early trials with Honda<\/i><\/p>\n

SAN JOSE, Calif.–(BUSINESS WIRE<\/a>)–
\nCadence (Nasdaq: CDNS) today introduced a new agent for Cadence\u00ae ChipStack\u2122 AI Super Agent that automates front\u2011end digital design and verification\u2014covering power, performance and area (PPA)-driven spec\u2011to\u2011RTL generation, RTL analysis, and refinement; all from natural language prompts. Building on the industry\u2019s first agentic workflow for front\u2011end design and verification announced<\/a> in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high\u2011quality RTL creation and optimization. In early evaluations, the RTL Generation Agent delivered an average of 24% area reduction and 18% power reduction versus pure foundation model code generation, while ensuring 100% functionally accurate RTL, underscoring the industry\u2019s most comprehensive agentic workflow for PPA-focused high-performance digital design and verification.<\/p>\n

This press release features multimedia. View the full release here: https:\/\/www.businesswire.com\/news\/home\/20260922021231\/en\/<\/a><\/p>\n

\"Building<\/p>\n

Building on the industry\u2019s first agentic workflow for front end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high quality RTL creation and optimization.<\/p>\n<\/div>\n

\n\u201cThese latest agentic AI advancements take us from AI\u2011assisted tools to coordinated agentic workflows that behave more like virtual design engineers with expert-level command of the underlying technologies,\u201d said Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. \u201cBy pairing agentic automation of spec-to-RTL and RTL refinement with our proven implementation and signoff engines, we enable customers to achieve better design outcomes with higher productivity and stronger correlation across the design flow, further extending Cadence\u2019s leadership in AI\u2011driven, end\u2011to\u2011end chip design.\u201d<\/p>\n

\nCadence\u2019s transformational approach to applying agentic AI to engineering design is founded on a hierarchy of solutions\u2014super agents orchestrate task-specific agents, which in turn use trusted electronic design automation (EDA) software, optimized for agentic workflows. The new RTL Generation Agent converts high\u2011level specification into production\u2011ready RTL optimized for PPA.<\/p>\n

Customer Validation from Honda<\/b><\/p>\n

\nEarly collaborations with Honda R&D demonstrate how these agentic AI capabilities translate into real\u2011world PPA and productivity gains on next\u2011generation SoCs.<\/p>\n

\nHonda is evaluating the RTL Generation Agent on advanced automotive SoCs, where safety\u2011critical requirements and tight power and cost envelopes demand highly optimized RTL.<\/p>\n

\n\u201cAs a key enabler of Software-Defined Vehicles (SDVs), AI technology for autonomous driving is advancing rapidly. However, the long development cycle of SoCs remains a major challenge. With the Cadence ChipStack AI Super Agent\u2019s RTL Generation Agent and AI-powered automation, Honda R&D is working to improve productivity from specification through RTL development,\u201d said Tomoya Nishino, chief engineer and general manager, Digital Engine Development Division, SDV R&D Center, Honda R&D Co., Ltd.<\/p>\n

Smarter RTL Updates and Early PPA Insight<\/b><\/p>\n

\nIn addition to new RTL creation within the RTL Generation Agent, Cadence is introducing technology for design updates to existing RTL based on new requirements. This RTL upgrade flow brings AI automation to accelerate RTL revision, enabling customers to rapidly adapt legacy RTL to new architecture requirements, new PPA targets and new functional requirements. Engineers describe changes at a high level, and the agents carry out the updates while analyzing and verifying PPA and functionality.<\/p>\n

Advancing Cadence\u2019s Agentic AI Vision<\/b><\/p>\n

\nThese enhancements build on Cadence\u2019s \u201cDesign for AI and AI for Design\u201d strategy highlighted at CadenceLIVE and Computex, further extending the company\u2019s leadership in AI\u2011driven chip design. From the initial ChipStack AI Super Agent launch through June\u2019s announcement<\/a> of the industry\u2019s first fully autonomous virtual engineer for chip design, and now today\u2019s RTL Generation Agent, Cadence continues to expand the scope of agentic workflows across the design stack. Together with the broader ChipStack, InnoStack and ViraStack AI Super Agent portfolio, they advance a scalable platform that applies AI across digital, analog and verification domains.<\/p>\n

Availability<\/b><\/p>\n

\nThe expanded ChipStack and InnoStack AI Super Agent capabilities are expected to be available to select early\u2011access customers in the fourth quarter of 2026.<\/p>\n

About Cadence<\/b><\/p>\n

\nCadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence\u2019s Intelligent System Design\u2122 strategy, are essential for the world\u2019s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics.<\/p>\n

\nIn 2025, Cadence was recognized by Fortune as one of the world\u2019s top 100 best companies to work for. Cadence solutions offer limitless opportunities.<\/p>\n

\n\u00a9 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com\/go\/trademarks<\/a> are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.<\/p>\n

\nCategory: Featured<\/p>\n

\"\"<\/p>\n

View source version on businesswire.com: <\/span>https:\/\/www.businesswire.com\/news\/home\/20260922021231\/en\/<\/a><\/span><\/p>\n

\nSteve Gartner
\n
513-479-4060
\n
sgartner@cadence.com<\/a><\/p>\n

KEYWORDS:<\/b> United States North America California<\/p>\n

INDUSTRY KEYWORDS:<\/b> Software Hardware Electronic Design Automation Automotive Artificial Intelligence Technology Vehicle Technology Semiconductor<\/p>\n

MEDIA:<\/b><\/p>\n\n\n\n\n\n\n\n
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\"Photo\"<\/td>\n<\/tr>\n
Building on the industry\u2019s first agentic workflow for front end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high quality RTL creation and optimization.<\/font><\/td>\n<\/tr>\n
Logo<\/b><\/font><\/td>\n<\/tr>\n
\"Logo\"<\/td>\n<\/tr>\n
<\/font><\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff\u2011grade quality and performance, validated in early trials with Honda SAN JOSE, Calif.–(BUSINESS WIRE)– Cadence (Nasdaq: CDNS) today introduced a new agent for Cadence\u00ae ChipStack\u2122 AI Super Agent that automates front\u2011end digital design and verification\u2014covering power, performance and area (PPA)-driven spec\u2011to\u2011RTL generation, RTL analysis, and refinement; all from natural language prompts. Building on the industry\u2019s first agentic workflow for front\u2011end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high\u2011quality RTL creation … <\/p>\n

Continue reading “Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-1005090","post","type-post","status-publish","format-standard","hentry"],"yoast_head":"\nCadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization - Market Newsdesk<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization - Market Newsdesk\" \/>\n<meta property=\"og:description\" content=\"Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff\u2011grade quality and performance, validated in early trials with Honda SAN JOSE, Calif.–(BUSINESS WIRE)– Cadence (Nasdaq: CDNS) today introduced a new agent for Cadence\u00ae ChipStack\u2122 AI Super Agent that automates front\u2011end digital design and verification\u2014covering power, performance and area (PPA)-driven spec\u2011to\u2011RTL generation, RTL analysis, and refinement; all from natural language prompts. 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Building on the industry\u2019s first agentic workflow for front\u2011end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high\u2011quality RTL creation … Continue reading \"Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization\"","og_url":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/","og_site_name":"Market Newsdesk","article_published_time":"2026-09-22T16:45:46+00:00","og_image":[{"url":"https:\/\/mms.businesswire.com\/media\/20260922021231\/en\/2908340\/4\/J65740_Stratus_AI_RTL_Agent_ChipStack_SM_1080x1350.jpg","type":"","width":"","height":""}],"author":"Newsdesk","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Newsdesk","Est. reading time":"5 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/#article","isPartOf":{"@id":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/"},"author":{"name":"Newsdesk","@id":"https:\/\/www.marketnewsdesk.com\/#\/schema\/person\/482f27a394d4fda80ecb5499e519d979"},"headline":"Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization","datePublished":"2026-09-22T16:45:46+00:00","mainEntityOfPage":{"@id":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/"},"wordCount":971,"image":{"@id":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/#primaryimage"},"thumbnailUrl":"https:\/\/mms.businesswire.com\/media\/20260922021231\/en\/2908340\/4\/J65740_Stratus_AI_RTL_Agent_ChipStack_SM_1080x1350.jpg","inLanguage":"en-US"},{"@type":"WebPage","@id":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/","url":"https:\/\/www.marketnewsdesk.com\/index.php\/cadence-expands-chipstack-ai-super-agent-with-a-new-agent-for-rtl-generation-and-early-ppa-optimization\/","name":"Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization - 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